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| PSD4000 Series PSD4235G2 Flash In-System-Programmable Peripherals for 16-Bit MCUs May, 2000 Beta Information 47280 Kato Road, Fremont, California 94538 Tel: 510-656-5400 Fax: 510-657-8495 800-TEAM-WSI (800-832-6974) Web Site: http://www.waferscale.com E-mail: info@waferscale.com PSD4000 Series PSD4235G2 Flash In-System-Programmable Peripherals for 16-Bit MCUs Table of Contents Introduction ........................................................................................................................................................................................1 In-System Programming (ISP) JTAG .......................................................................................................................................2 In-Application re-Programming (IAP) .......................................................................................................................................2 Key Features......................................................................................................................................................................................3 PSD4000 Family ................................................................................................................................................................................3 Block Diagram....................................................................................................................................................................................4 Architectural Overview .......................................................................................................................................................................5 Memory ....................................................................................................................................................................................5 PLDs.........................................................................................................................................................................................5 I/O Ports ...................................................................................................................................................................................5 Microcontroller Bus Interface....................................................................................................................................................6 ISP via JTAG Port ....................................................................................................................................................................6 In-System Programming...........................................................................................................................................................6 In-Application re-Programming (IAP) .......................................................................................................................................6 Page Register...........................................................................................................................................................................6 Power Management Unit ..........................................................................................................................................................6 Development System.........................................................................................................................................................................7 Pin Descriptions .................................................................................................................................................................................8 Register Description and Address Offset .........................................................................................................................................11 Register Bit Definition ......................................................................................................................................................................12 Functional Blocks.............................................................................................................................................................................16 Memory Blocks .......................................................................................................................................................................16 Main Flash and Secondary Flash Memory Description ...................................................................................................16 SRAM...............................................................................................................................................................................27 Memory Chip Selects .......................................................................................................................................................27 Page Register ..................................................................................................................................................................30 Memory ID Registers .......................................................................................................................................................31 PLDs.......................................................................................................................................................................................32 Decode PLD (DPLD)........................................................................................................................................................34 Complex PLD (CPLD) ......................................................................................................................................................34 Microcontroller Bus Interface..................................................................................................................................................42 Interface to a Multiplexed Bus..........................................................................................................................................42 Interface to a Non-multiplexed Bus..................................................................................................................................42 Data Byte Enable Reference ...........................................................................................................................................44 Microcontroller Interface Examples..................................................................................................................................45 I/O Ports .................................................................................................................................................................................50 General Port Architecture ................................................................................................................................................50 Port Operating Modes......................................................................................................................................................52 Port Configuration Registers (PCRs) ...............................................................................................................................55 Port Data Registers..........................................................................................................................................................58 Ports A, B and C - Functionality and Structure ...............................................................................................................59 Port D - Functionality and Structure ................................................................................................................................60 Port E - Functionality and Structure ................................................................................................................................60 Port F - Functionality and Structure ................................................................................................................................61 Port G - Functionality and Structure................................................................................................................................61 For additional information, Call 800-TEAM-WSI (800-832-6974). Fax: 510-657-8495 Web Site: http://www.waferscale.com E-mail: info@waferscale.com i PSD4000 Series PSD4235G2 Flash In-System-Programmable Peripherals for 16-Bit MCUs Table of Contents Power Management ...............................................................................................................................................................62 Automatic Power Down (APD) Unit and Power Down Mode ...........................................................................................62 Other Power Savings Options..........................................................................................................................................66 Reset and Power On Requirement ..................................................................................................................................67 Programming In-Circuit using the JTAG-ISP Interface...........................................................................................................68 Standard JTAG Signals ...................................................................................................................................................69 JTAG Extensions .............................................................................................................................................................70 Security and Flash Memories Protection .........................................................................................................................70 Absolute Maximum Ratings .............................................................................................................................................................71 Operating Range..............................................................................................................................................................................71 Recommended Operating Conditions..............................................................................................................................................71 AC/DC Parameters ..........................................................................................................................................................................72 Example of Typical Power Calculation at Vcc = 5..0 V...........................................................................................................73 Example of Typical Power Calculation at Vcc = 5..0 V in Turbo Off Mode.............................................................................74 DC Characteristics (5 V 10% versions).........................................................................................................................................75 GPLD Timing Parameters (5 V 10% versions) .............................................................................................................................76 Microcontroller Interface - AC/DC Parameters (5 V 10% versions) .............................................................................................79 DC Characteristics (3.0 V to 3.6 V versions) ...................................................................................................................................84 GPLD Timing Parameters (3.0 V to 3.6 V versions) .......................................................................................................................85 Microcontroller Interface - AC/DC Parameters (3.0 V to 3.6 V versions) .......................................................................................88 Timing Diagrams ..............................................................................................................................................................................93 Pin Capacitance.............................................................................................................................................................................100 AC Testing Input/Output Waveforms .............................................................................................................................................100 AC Testing Load Circuit .................................................................................................................................................................100 Programming .................................................................................................................................................................................100 Pin Assignments ............................................................................................................................................................................101 Package Information ......................................................................................................................................................................102 Selector Guide ...............................................................................................................................................................................104 Part Number Construction .............................................................................................................................................................105 Ordering Information ......................................................................................................................................................................105 Document Revisions ......................................................................................................................................................................106 Worldwide Sales, Service and Technical Support .........................................................................................................................108 For additional information, Call 800-TEAM-WSI (800-832-6974). Fax: 510-657-8495 Web Site: http://www.waferscale.com E-mail: info@waferscale.com ii PSD4000 Series Beta Information For additional information, Call 800-TEAM-WSI (800-832-6974). Fax: 510-657-8495 Web Site: http://www.waferscale.com E-mail: info@waferscale.com iii Programmable Peripheral PSD4000 Series PSD4235G2 Flash In-System-Programmable Peripherals for 16-Bit MCUs Beta Information 1.0 Introduction The PSD4000 series of Programmable Microcontroller (MCU) Peripherals brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD4000 devices combine many of the peripheral functions found in MCU based applications: * 4 Mbit of Flash memory * A secondary Flash memory for boot or data * Over 3,000 gates of Flash programmable logic * 64 Kbit SRAM * Reconfigurable I/O ports * Programmable power management. PSD4000 series devices integrate an optimized "microcontroller macrocell" logic architecture called the MicroCellTM. The MicroCell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus and the internal PSD registers to simplify communication between the MCU and other supporting devices. 1 PSD4000 Series Beta Information The PSD4235G2 family offers two methods to program PSD Flash memory while the PSD is soldered to a circuit board. 1.0 Introduction (Cont.) In-System Programming (ISP) via JTAG An IEEE 1149.1 compliant JTAG-ISP interface is included on the PSD enabling the entire device (both flash memories, the PLD, and all configuration) to be rapidly programmed while soldered to the circuit board. This requires no MCU participation, which means the PSD can be programmed anytime, even while completely blank. The innovative JTAG interface to flash memories is an industry first, solving key problems faced by designers and manufacturing houses, such as: * First time programming - How do I get firmware into the flash the very first time? JTAG is the answer, program the PSD while blank with no MCU involvement. * Inventory build-up of pre-programmed devices - How do I maintain an accurate count of pre-programmed flash memory and PLD devices based on customer demand? How many and what version? JTAG is the answer, build your hardware with blank PSDs soldered directly to the board and then custom program just before they are shipped to customer. No more labels on chips and no more wasted inventory. * Expensive sockets - How do I eliminate the need for expensive and unreliable sockets? JTAG is the answer. Solder the PSD directly to the circuit board. Program first time and subsequent times with JTAG. No need to handle devices and bend the fragile leads. In-Application re-Programming (IAP) Two independent flash memory arrays are included so the MCU can execute code from one memory while erasing and programming the other. Robust product firmware updates in the field are possible over any communication channel (CAN, Ethernet, UART, J1850, etc) using this unique architecture. Designers are relieved of these problems: * Simultaneous read and write to flash memory - How can the MCU program the same memory from which it is executing code? It cannot. The PSD allows the MCU to operate the two flash memories concurrently, reading code from one while erasing and programming the other during IAP. * Complex memory mapping - How can I map these two memories efficiently? A Programmable Decode PLD is embedded in the PSD. The concurrent PSD memories can be mapped anywhere in MCU address space, segment by segment with extremely high address resolution. As an option, the secondary flash memory can be swapped out of the system memory map when IAP is complete. A built-in page register breaks the MCU address limit. * Separate program and data space - How can I write to flash memory while it resides in "program" space during field firmware updates, my 80C51XA won't allow it! The flash PSD provides means to "reclassify" flash memory as "data" space during IAP, then back to "program" space when complete. PSDsoft - Waferscale's software development tool - guides you through the design process step-by-step making it possible to complete an embedded MCU design capable of ISP/IAP in just hours. Select your MCU and PSDsoft will take you through the remainder of the design with point and click entry, covering...PSD selection, pin definitions, programmable logic inputs and outputs, MCU memory map definition, ANSI C code generation for your MCU, and merging your MCU firmware with the PSD design. When complete, two different device programmers are supported directly from PSDsoft - FlashLINK (JTAG) and PSDpro. The PSD4235G2 is available in an 80-pin TQFP package. Please refer to the revision block at the end of this document for updated information. 2 Beta Information PSD4000 Series 2.0 Key Features A simple interface to 16-bit microcontrollers that use either multiplexed or non-multiplexed busses. The bus interface logic uses the control signals generated by the microcontroller automatically when the address is decoded and a read or write is performed. A partial list of the MCU families supported include: * Intel 80196, 80186, and 80386EX * Motorola 68HC16, 68HC12, 683XX, and MC2001 * Philips 80C51XA * Infineon C16X devices * Hitachi H8 4 Mbit Flash memory. This is the main Flash memory. It is divided into eight equal-sized blocks that can be accessed with user-specified addresses. Internal secondary 256 Kbit Flash boot memory. It is divided into four equal-sized blocks that can be accessed with user-specified addresses. This secondary memory brings the ability to execute code and update the main Flash concurrently. 64 Kbit SRAM. The SRAM's contents can be protected from a power failure by connecting an external battery. CPLD with 16 Output MicroCells (OMCs) and 24 Input MicroCells (IMCs). The CPLD may be used to efficiently implement a variety of logic functions for internal and external control. Examples include state machines, loadable shift registers, and loadable counters. The CPLD can also generate eight external chip selects. Decode PLD (DPLD) that decodes address for selection of internal memory blocks. 52 individually configurable I/O port pins that can be used for the following functions: * MCU I/Os * PLD I/Os * Latched MCU address output * Special function I/Os. * I/O ports may be configured as open-drain outputs. Standby current as low as 50 A for 5 V devices. Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP). With it, you can program a blank device or reprogram a device in the factory or the field. Internal page register that can be used to expand the microcontroller address space by a factor of 256. Internal programmable Power Management Unit (PMU) that supports a low power mode called Power Down Mode. The PMU can automatically detect a lack of microcontroller activity and put the PSD4000 into Power Down Mode. Erase/Write cycles: * Flash memory - 100,000 minimum * PLD - 1,000 minimum * 15 year data retention 3.0 PSD4000 Series Table 1. PSD4000 Product Matrix Part # PSD4000 Series PSD4000 I/O Pins 52 52 Flash Serial ISP PLD Input Output PLD JTAG-ISP Inputs Macrocells Macrocells Outputs Port 66 82 24 16 24 24 Yes Yes Flash Main Memory Kbit 8 Sectors 4096 4096 Boot Memory Kbit (4 Sectors) 256 256 Device PSD4135G2* PSD4235G2 SRAM Kbit 64 64 Supply Voltage 5V 5V *See PSD4135G2 Data Sheet. 3 4 ADDRESS/DATA/CONTROL BUS PLD INPUT BUS PAGE REGISTER EMBEDDED ALGORITHM 8 SECTORS POWER MANGMT UNIT 4 MBIT MAIN FLASH MEMORY PSD4000 Series Figure 1. PSD4000 Block Diagram VSTDBY (PE6) CNTL0, CNTL1, CNTL2 SECTOR SELECTS FLASH DECODE PLD (DPLD) 256 KBIT SECONDARY FLASH MEMORY (BOOT OR DATA) 4 SECTORS PROG. MCU BUS INTRF. 82 SECTOR SELECTS SRAM SELECT PERIP I/O MODE SELECTS CSIOP RUNTIME CONTROL AND I/O REGISTERS 8 EXT CS to PORT C or F 16 OUTPUT MICROCELLS PORT A & B 24 INPUT MICROCELLS CLKIN PORT A ,B & C 64 KBIT BATTERY BACKUP SRAM PROG. PORT PORT A PROG. PORT PORT B PA0 - PA7 AD0 - AD15 ADIO PORT PB0 - PB7 82 FLASH ISP CPLD (CPLD) PF0 - PF7 PROG. PORT PROG. PORT PORT C PC0 - PC7 PORT F MICROCELL FEEDBACK OR PORT INPUT CLKIN PORT F PROG. PORT PORT D PD0 - PD3 PG0 - PG7 PROG. PORT PORT G PROG. PORT PORT E PLD, CONFIGURATION & FLASH MEMORY LOADER JTAG SERIAL CHANNEL PE0 - PE7 CLKIN GLOBAL CONFIG. & SECURITY Beta Information *Additional address lines can be brought into PSD via Port A, B, C, D or F. Beta Information PSD4000 Series PSD4000 devices contain several major functional blocks. Figure 1 on page 3 shows the architecture of the PSD4000 device family. The functions of each block are described briefly in the following sections. Many of the blocks perform multiple functions and are user configurable. 4.0 PSD4000 Architectural Overview 4.1 Memory The PSD4000 contains the following memories: * 4 Mbit Flash * A secondary 256 Kbit Flash memory for boot or data * 64 Kbit SRAM. Each of the memories is briefly discussed in the following paragraphs. A more detailed discussion can be found in section 9. The 4 Mbit Flash is the main memory of the PSD4000. It is divided into eight equally-sized sectors that are individually selectable. The 256 Kbit secondary Flash memory is divided into four equally-sized sectors. Each sector is individually selectable. The 64 Kbit SRAM is intended for use as a scratchpad memory or as an extension to the microcontroller SRAM. If an external battery is connected to the PSD4000's Vstby pin, data will be retained in the event of a power failure. Each block of memory can be located in a different address space as defined by the user. The access times for all memory types includes the address latching and DPLD decoding time. 4.2 PLDs The device contains two PLD blocks, each optimized for a different function, as shown in Table 2. The functional partitioning of the PLDs reduces power consumption, optimizes cost/performance, and eases design entry. The Decode PLD (DPLD) is used to decode addresses and generate chip selects for the PSD4000 internal memory and registers. The CPLD can implement user-defined logic functions. The DPLD has combinatorial outputs. The CPLD has 16 Output MicroCells and 8 combinatorial outputs. The PSD4000 also has 24 Input MicroCells that can be configured as inputs to the PLDs. The PLDs receive their inputs from the PLD Input Bus and are differentiated by their output destinations, number of Product Terms, and MicroCells. The PLDs consume minimal power by using Zero-Power design techniques. The speed and power consumption of the PLD is controlled by the Turbo Bit in the PMMR0 register and other bits in the PMMR2 registers. These registers are set by the microcontroller at runtime. There is a slight penalty to PLD propagation time when invoking the non-Turbo bit. 4.3 I/O Ports The PSD4000 has 52 I/O pins divided among seven ports (Port A, B, C, D, E, F and G). Each I/O pin can be individually configured for different functions. Ports can be configured as standard MCU I/O ports, PLD I/O, or latched address outputs for microcontrollers using multiplexed address/data busses. The JTAG pins can be enabled on Port E for In-System Programming (ISP). Ports F and G can also be configured as a data port for a non-multiplexed bus. Table 2. PLD I/O Table Name Decode PLD Complex PLD Abbreviation DPLD CPLD Inputs 82 82 Outputs 17 24 Product Terms 43 150 5 PSD4000 Series Beta Information PSD4000 Architectural Overview (cont.) 4.4 Microcontroller Bus Interface The PSD4000 easily interfaces with most 16-bit microcontrollers that have either multiplexed or non-multiplexed address/data busses. The device is configured to respond to the microcontroller's control signals, which are also used as inputs to the PLDs. Section 9.3.5 contains microcontroller interface examples. 4.5 ISP via JTAG Port In-System Programming can be performed through the JTAG pins on Port E. This serial interface allows complete programming of the entire PSD4000 device. A blank device can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can be multiplexed with other functions on Port E. Table 3 indicates the JTAG signals pin assignments. 4.6 In-System Programming (ISP) Using the JTAG signals on Port E, the entire PSD4000 (memory, logic, cofiguration) device can be programmed or erased without the use of the microcontroller. Table 3. JTAG Signals on Port E Port E Pins PE0 PE1 PE2 PE3 PE4 PE5 JTAG Signal TMS TCK TDI TDO TSTAT TERR 4.7 In-Application re-Programming (IAP) The main Flash memory can also be programmed in-system by the microcontroller executing the programming algorithms out of the secondary Flash memory, or SRAM (IAP). The secondary Flash boot memory can be programmed the same way by executing out of the main Flash memory. Table 4 indicates which programming methods can program different functional blocks of the PSD4000. Table 4. Methods of Programming Different Functional Blocks of the PSD4000 Functional Block Main Flash memory Flash Boot memory PLD Array (DPLD and CPLD) PSD Configuration JTAG-ISP Yes Yes Yes Yes Device Programmer Yes Yes Yes Yes IAP Yes Yes No No 4.8 Page Register The eight-bit Page Register expands the address range of the microcontroller by up to 256 times.The paged address can be used as part of the address space to access external memory and peripherals or internal memory and I/O. The Page Register can also be used to change the address mapping of blocks of Flash memory into different memory spaces IAP. 4.9 Power Management Unit The Power Management Unit (PMU) in the PSD4000 gives the user control of the power consumption on selected functional blocks based on system requirements. The PMU includes an Automatic Power Down unit (APD) that will turn off device functions due to microcontroller inactivity. The APD unit has a Power Down Mode that helps reduce power consumption. The PSD4000 also has some bits that are configured at run-time by the MCU to reduce power consumption of the CPLD. The turbo bit in the PMMR0 register can be turned off and the CPLD will latch its outputs and go to standby until the next transition on its inputs. Additionally, bits in the PMMR2 register can be set by the MCU to block signals from entering the CPLD to reduce power consumption. See section 9.5. 6 Beta Information PSD4000 Series The PSD4000 series is supported by PSDsoft a Windows-based (95, 98, NT) software development tool. A PSD design is quickly and easily produced in a point and click environment. The designer does not need to enter Hardware Definition Language (HDL) equations (unless desired) to define PSD pin functions and memory map information. The general design flow is shown in Figure 2 below. PSDsoft is available from our web site (www.waferscale.com) or other distribution channels. PSDsoft directly supports two low cost device programmers from Waferscale, PSDpro and FlashLINK (JTAG). Both of these programmers may be purchased through your local rep/distributor, or directly from our web site using a credit card. The PSD4000 is also supported by third party device programmers, see web site for current list. 5.0 Development System Figure 2. PSDsoft Development Tool Choose MCU and PSD Automatically Configures MCU bus interface and other PSD attributes. Define PSD Pin and Node functions Point and click definition of PSD pin functions, internal nodes, and MCU system memory map. Define General Purpose Logic in CPLD Point and click definition of combinatorial and registered logic in CPLD. Access to HDL is available if needed. C Code Generation Generate C Code Specific to PSD Functions Merge MCU Firmware with PSD Configuration A composite object file is created containing MCU firmware and PSD configuration. MCU Firmware Hex or S-Record format User's choice of Microcontroller Compiler/Linker *.OBJ FILE Waferscale PSD Programmer PSDPro or FlashLink (JTAG) *.OBJ file available for 3rd party programmers (Conventional or JTAG-ISP) 7 PSD4000 Series Beta Information The following table describes the pin names and pin functions of the PSD4000. Pins that have multiple names and/or functions are defined using PSDsoft. Pin* (TQFP Pkg.) 3-7 10-12 6.0 Table 5. PSD4000 Pin Descriptions Pin Name ADIO0-7 Type I/O Description This is the lower Address/Data port. Connect your MCU address or address/data bus according to the following rules: 1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect AD[0:7] to this port. 2. If your MCU does not have a multiplexed address/data bus, connect A[0:7] to this port. 3. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this port. ALE or AS latches the address. The PSD drives data out only if the read signal is active and one of the PSD functional blocks was selected. The addresses on this port are passed to the PLDs. This is the upper Address/Data port. Connect your MCU address or address/data bus according to the following rules: 1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the upper address bits, connect AD[8:15] to this port. 2. If your MCU does not have a multiplexed address/data bus, connect A[8:15] to this port. 3. If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to this port. ALE or AS latches the address. The PSD drives data out only if the read signal is active and one of the PSD functional blocks was selected. The addresses on this port are passed to the PLDs. The following control signals can be connected to this port, based on your MCU: 1. WR -- active-low write input. 2. R_W -- active-high read/active low write input. 3. WRL -- Write to low byte, active low This pin is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. The following control signals can be connected to this port, based on your MCU: 1. RD -- active-low read input. 2. E -- E clock input. 3. DS -- active-low data strobe input. 4. LDS -- Strobe for low data byte, active low. This pin is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. Read or other Control input pin with multiple configurations. Depending on the MCU interface selected, this pin can be: 1. PSEN -- Program Select enable, active low in code fetch bus cycle (80C51XA mode). 2. BHE -- High byte enable, 16-bit data bus 3. UDS -- Strobe for high data byte, 16-bit data bus mode, active low 4. SIZ0 -- Byte enable input 5. LSTRB -- Low strobe input. This pin is also connected to PLD as input. ADIO8-15 13-20 I/O CNTL0 59 I CNTL1 60 I CNTL2 40 I 8 Beta Information PSD4000 Series Pin* (TQFP Pin Name Pkg.) Reset 39 Table 5. PSD4000 Pin Descriptions (cont.) Type I Description Active low input. Resets I/O Ports PLD MicroCells, some of the configuration registers and JTAG registers. Must be active at power up. Reset also aborts the Flash programming/erase cycle that is in progress. Port A, PA0-7. This port is pin configurable and has multiple functions: 1. MCU I/O -- standard output or input port 2. CPLD MicroCell (McellA0-7) output. 3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16 and above). Port B, PB0-7. This port is pin configurable and has multiple functions: 1. MCU I/O -- standard output or input port. 2. CPLD MicroCell (McellB0-7 output. 3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16 and above). Port C, PC0-7. This port is pin configurable and has multiple functions: 1. MCU I/O -- standard output or input port. 2. External chip select (ECS0-7) output. 3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16 and above). Port D pin PD0 can be configured as: 1. ALE or AS input -- latches addresses on ADIO0-15 pins 2. AS input -- latches addresses on ADIO0-15 pins on the rising edge. 3. MCU I/O 4. Transparent PLD input (can also be PLD input for address A16 and above). Port D pin PD1 can be configured as: 1. MCU I/O 2. Transparent PLD input (can also be PLD input for address A16 and above). 3. CLKIN clock input -- clock input to the CPLD MicroCells, the APD power down counter and CPLD AND Array. Port D pin PD2 can be configured as: 1. MCU I/O 2. Transparent PLD input (can also be PLD input for address A16 and above). 3. CSI input -- chip select input. When low, the CSI enables the internal PSD memories and I/O. When high, the internal memories are disabled to conserve power. CSI trailing edge can get the part out of power-down mode. Port D pin PD3 can be configured as: 1. MCU I/O 2. Transparent PLD input (can also be PLD input for address A16 and above). 3. WRH -- for 16-bit data bus, write to high byte, active low. Port E, PE0. This port is pin configurable and has multiple functions: 1. MCU I/O -- standard output or input port. 2. Latched address output. 3. TMS input for JTAG-ISP interface. PA0-PA7 51-58 I/O CMOS or Open Drain PB0-PB7 61-68 I/O CMOS or Open Drain PC0-PC7 41-48 I/O CMOS or Slew Rate PD0 79 I/O CMOS or Open Drain PD1 80 I/O CMOS or Open Drain PD2 1 I/O CMOS or Open Drain PD3 2 I/O CMOS or Open Drain I/O CMOS or Open Drain PE0 71 9 PSD4000 Series Beta Information Pin* (TQFP Pin Name Pkg.) PE1 72 Table 5. PSD4000 Pin Descriptions (cont.) Type I/O CMOS or Open Drain I/O CMOS or Open Drain I/O CMOS or Open Drain I/O CMOS or Open Drain Description Port E, PE1. This port is pin configurable and has multiple functions: 1. MCU I/O -- standard output or input port. 2. Latched address output. 3. TCK input for JTAG-ISP interface (Schmidt Trigger). Port E, PE2. This port is pin configurable and has multiple functions: 1. MCU I/O -- standard output or input port. 2. Latched address output. 3. TDI input for JTAG-ISP interface. Port E, PE3. This port is pin configurable and has multiple functions: 1. MCU I/O -- standard output or input port. 2. Latched address output. 3. TDO output for JTAG-ISP interface. Port E, PE4. This port is pin configurable and has multiple functions: 1. MCU I/O -- standard output or input port. 2. Latched address output. 3. TSTAT output for the ISC interface. 4. Rdy/Bsy -- for in-circuit Parallel Programming. Port E, PE5. This port is pin configurable and has multiple functions: 1. MCU I/O -- standard output or input port. 2. Latched address output. 3. TERR active low output for ISC interface. Port E, PE6. This port is pin configurable and has multiple functions: 1. MCU I/O -- standard output or input port. 2. Latched address output. 3. Vstby -- SRAM standby voltage input for battery backup SRAM Port E, PE7. This port is pin configurable and has multiple functions: 1. MCU I/O -- standard output or input port. 2. Latched address output. 3. Vbaton -- battery backup indicator output. Goes high when power is drawn from an external battery. Port F, PF0-7. This port is pin configurable and has multiple functions: 1. MCU I/O -- standard output or input port. 2. External chip select (ECS0-7) output, or input to CPLD. 3. Latched address outputs. 4. As address A1-3 inputs in 80C51XA mode (PF0 is grounded 5. As data bus port (D0-7) in non-multiplexed bus configuration 6. Peripheral I/O mode 7. MCU reset mode. Port G, PG0-7. This port is pin configurable and has multiple functions: 1. MCU I/O -- standard output or input port. 2. Latched address outputs. 3. As data bus port (D8-15) in non-multiplexed bus configuration. 4. MCU reset mode. PE2 73 PE3 74 PE4 75 PE5 76 I/O CMOS or Open Drain I/O CMOS or Open Drain PE6 77 PE7 78 I/O CMOS or Open Drain PF0-PF7 31-38 I/O CMOS or Open Drain PG0-PG7 21-28 I/O CMOS or Open Drain GND 8,30, 49,50, 70 9,29, 69 VCC 10 Beta Information PSD4000 Series Table 6 shows the offset addresses to the PSD4000 registers relative to the CSIOP base address. The CSIOP space is the 256 bytes of address that is allocated by the user to the internal PSD4000 registers. Table 6 provides brief descriptions of the registers in CSIOP space. For a more detailed description, refer to section 9. 7.0 PSD4000 Register Description and Address Offset Table 6. Register Address Offset Register Name Data In Control Data Out Direction 04 06 05 07 14 16 15 17 Port A 00 Port B 01 Port C 10 Port D 11 Port E 30 32 34 36 Port F 40 42 44 46 Port G 41 43 45 47 Other* Description Reads Port pin as input, MCU I/O input mode Selects mode between MCU I/O or Address Out Stores data for output to Port pins, MCU I/O output mode Configures Port pin as input or output Configures Port pins as either CMOS or Open Drain on some pins, while selecting high slew rate on other pins. Reads Input MicroCells Reads the status of the output enable to the I/O Port driver Read - reads output of MicroCells A Write - loads Microcell Flip-Flops Read - reads output of MicroCells B Write - loads Microcell Flip-Flops Blocks writing to the Output MicroCells A Blocks writing to the Output MicroCells B Read only - Flash Sector Protection Read only - PSD Security and Flash Boot Sector Protection Enables JTAG Port Power Management Register 0 Power Management Register 2 Page Register Places PSD memory areas in Program and/or Data space on an individual basis. Read only - Flash and SRAM size Read only - Boot type and size Drive Select 08 09 18 19 38 48 49 Input MicroCell Enable Out 0A 0C 0B 0D 1C 1A 4C Output MicroCells A 20 Output MicroCells B Mask MicroCells A Mask MicroCells B Flash Protection Flash Boot Protection JTAG Enable PMMR0 PMMR2 Page VM 22 21 23 C0 C2 C7 B0 B4 E0 E2 Memory_ID0 Memory_ID1 F0 F1 11 PSD4000 Series Beta Information All the registers in the PSD4000 are included here for reference. Detail description of the registers are found in the Functional Block section of the Data Sheet. Data In Registers - Port A, B, C, D, E, F and G Bit 7 Port Pin 7 8.0 Register Bit Definition Bit 6 Port Pin 6 Bit 5 Port Pin 5 Bit 4 Port Pin 4 Bit 3 Port Pin 3 Bit 2 Port Pin 2 Bit 1 Bit 0 Port Pin 1 Port Pin 0 Bit definitions: Read only registers, read Port pin status when Port is in MCU I/O input Mode. Data Out Registers - Port A, B, C, D, E, F and G Bit 7 Port Pin 7 Bit 6 Port Pin 6 Bit 5 Port Pin 5 Bit 4 Port Pin 4 Bit 3 Port Pin 3 Bit 2 Port Pin 2 Bit 1 Bit 0 Port Pin 1 Port Pin 0 Bit definitions: Latched data for output to Port pin when pin is configured in MCU I/O output mode. Direction Registers - Port A, B, C, D, E, F and G Bit 7 Port Pin 7 Bit 6 Port Pin 6 Bit 5 Port Pin 5 Bit 4 Port Pin 4 Bit 3 Port Pin 3 Bit 2 Port Pin 2 Bit 1 Bit 0 Port Pin 1 Port Pin 0 Bit definitions: Set Register Bit to 0 = configure corresponding Port pin in Input mode (default). Set Register Bit to 1 = configure corresponding Port pin in Output mode. Control Registers - Ports E, F and G Bit 7 Port Pin 7 Bit 6 Port Pin 6 Bit 5 Port Pin 5 Bit 4 Port Pin 4 Bit 3 Port Pin 3 Bit 2 Port Pin 2 Bit 1 Bit 0 Port Pin 1 Port Pin 0 Bit definitions: Set Register Bit to 0 = configure corresponding Port pin in MCU I/O mode (default). Set Register Bit to 1 = configure corresponding Port pin in Latched Address Out mode. Drive Registers - Ports A, B, D, E, and G Bit 7 Port Pin 7 Bit 6 Port Pin 6 Bit 5 Port Pin 5 Bit 4 Port Pin 4 Bit 3 Port Pin 3 Bit 2 Port Pin 2 Bit 1 Bit 0 Port Pin 1 Port Pin 0 Bit definitions: Set Register Bit to 0 = configure corresponding Port pin in CMOS output driver (default). Set Register Bit to 1 = configure corresponding Port pin in Open Drain output driver. Drive Registers - Ports C and F Bit 7 Port Pin 7 Bit 6 Port Pin 6 Bit 5 Port Pin 5 Bit 4 Port Pin 4 Bit 3 Port Pin 3 Bit 2 Port Pin 2 Bit 1 Bit 0 Port Pin 1 Port Pin 0 Bit definitions: Set Register Bit to 0 = configure corresponding Port pin as CMOS output driver (default). Set Register Bit to 1 = configure corresponding Port pin in Slew Rate mode. Enable Out Registers - Ports A, B, C and F Bit 7 Port Pin 7 Bit 6 Port Pin 6 Bit 5 Port Pin 5 Bit 4 Port Pin 4 Bit 3 Port Pin 3 Bit 2 Port Pin 2 Bit 1 Bit 0 Port Pin 1 Port Pin 0 Bit definitions: Read Only Registers Register Bit 12 Beta Information PSD4000 Series Input MicroCells - Ports A, B and C Bit 7 IMcell7 8.0 Register Bit Definition (cont.) Bit 6 IMcell6 Bit 5 IMcell5 Bit 4 IMcell4 Bit 3 IMcell3 Bit 2 IMcell2 Bit 1 IMcell1 Bit 0 IMcell0 Bit definitions: Read Only Registers Read Input MicroCell[7:0] status on Ports A, B and C. Output MicroCells A Register Bit 7 Mcella7 Bit 6 Mcella6 Bit 5 Mcella5 Bit 4 Mcella4 Bit 3 Mcella3 Bit 2 Mcella2 Bit 1 Mcella1 Bit 0 Mcella0 Bit definitions: Write Register: Load MicroCellA[7:0] with 0 or 1. Read Register: Read MicroCellA[7:0] output status. Output MicroCells B Register Bit 7 Mcellb7 Bit 6 Mcellb6 Bit 5 Mcellb5 Bit 4 Mcellb4 Bit 3 Mcellb3 Bit 2 Mcellb2 Bit 1 Mcellb1 Bit 0 Mcellb0 Bit definitions: Write Register: Load MicroCellB[7:0] with 0 or 1. Read Register: Read MicroCellB[7:0] output status. Mask MicroCells A Register Bit 7 Mcella7 Bit 6 Mcella6 Bit 5 Mcella5 Bit 4 Mcella4 Bit 3 Mcella3 Bit 2 Mcella2 Bit 1 Mcella1 Bit 0 Mcella0 Bit definitions: Register Bit Mcellb7 Bit 6 Mcellb6 Bit 5 Mcellb5 Bit 4 Mcellb4 Bit 3 Mcellb3 Bit 2 Mcellb2 Bit 1 Mcellb1 Bit 0 Mcellb0 Bit definitions: Register Bit Sec7_Prot Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot Bit definitions: Read Only Register Sec_Prot 1 = Flash Sector is write protected. Sec_Prot 0 = Flash Sector is not write protected. Flash Boot Protection Register Bit 7 Security_Bit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 * * * Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot Bit definitions: Sec_Prot 1 = Boot Block Sector is write protected. Sec_Prot 0 = Boot Block Sector is not write protected. Security_Bit 0 = Security Bit in device has not been set. 1 = Security Bit in device has been set. 13 PSD4000 Series Beta Information JTAG Enable Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 JTAG_Enable 8.0 Register Bit Definition (cont.) * * * * * * * Bit definitions: JTAG_Enable 1 = JTAG Port is Enabled. 0 = JTAG Port is Disabled. Page Register Bit 7 Pgr7 Bit 6 Pgr6 Bit 5 Pgr5 Bit 4 Pgr4 Bit 3 Pgr3 Bit 2 Pgr2 Bit 1 Pgr1 Bit 0 Pgr0 Bit definitions: Configure Page input to PLD. Default Pgr[7:0] = 00. PMMR0 Register Bit 7 Bit 6 Bit 5 PLD Mcells clk Bit 4 PLD array-clk Bit 3 PLD Turbo Bit 2 Bit 1 APD enable Bit 0 * * * * *Not used bit should be set to zero. Bit definitions: (default is 0) Bit 1 0 = Automatic Power Down (APD) is disabled. 1 = Automatic Power Down (APD) is enabled. Bit 3 0 = PLD Turbo is on. 1 = PLD Turbo is off, saving power. Bit 4 0 = CLKIN input to the PLD AND array is connected. Every CLKIN change will power up the PLD when Turbo bit is off. 1 = CLKIN input to PLD AND array is disconnected, saving power. Bit 5 0 = CLKIN input to the PLD MicroCells is connected. 1 = CLKIN input to the PLD MicroCells is disconnected, saving power. PMMR2 Register Bit 7 Bit 6 PLD array WRh Bit 5 PLD array Ale Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLD array Addr * PLD PLD PLD array Cntl2 array Cntl1 array Cntl0 * *Not used bit should be set to zero. Bit definitions (default is 0): Bit 0 0 = Address A[7:0] are connected into the PLD array. 1 = Address A[7:0] are blocked from the PLD array, saving power. Note: in XA mode, A3-0 come from PF3-0 and A7-4 come from ADIO7-4. Bit 2 0 = Cntl0 input to the PLD AND array is connected. 1 = Cntl0 input to the PLD AND array is disconnected, saving power. Bit 3 0 = Cntl1 input to the PLD AND array is connected. 1 = Cntl1 input to the PLD AND array is disconnected, saving power. Bit 4 0 = Cntl2 input to the PLD AND array is connected. 1 = Cntl2 input to the PLD AND array is disconnected, saving power. Bit 5 0 = Ale input to the PLD AND array is connected. 1 = Ale input to the PLD AND array is disconnected, saving power. Bit 6 0 = WRh/DBE input to the PLD AND array is connected. 1 = WRh/DBE input to the PLD AND array is disconnected, saving power. 14 Beta Information PSD4000 Series VM Register Bit 7 Periphmode 8.0 Register Bit Definition (cont.) Bit 6 Bit 5 Bit 4 FL_data Bit 3 Boot_data Bit 2 FL_code Bit 1 Bit 0 * * Boot_code SR_code Note: Upon reset, Bit1-Bit4 are loaded to configurations selected by the user in PSDsoft. Bit 0 and Bit 7 are always cleared by reset. Bit 0 to Bit 4 are active only when the device is configured in Philips 80C51XA mode. * Not used bit should be set to zero Bit definitions: Bit 0 0 = PSEN can't access SRAM in 80C51XA modes. 1 = PSEN can access SRAM in 80C51XA modes. Bit 1 0 = PSEN can't access Boot in 80C51XA modes. 1 = PSEN can access Boot in 80C51XA modes. Bit 2 0 = PSEN can't access main Flash in 80C51XA modes. 1 = PSEN can access main Flash in 80C51XA modes. Bit 3 0 = RD can't access Boot in 80C51XA modes. 1 = RD can access Boot in 80C51XA modes. Bit 4 0 = RD can't access main Flash in 80C51XA modes. 1 = RD can access main Flash in 80C51XA modes. Bit 7 0 = Peripheral mode of Port F is disabled. 1 = Peripheral mode of Port F is enabled. Memory_ID0 Register Bit 7 S_size 3 Bit 6 S_size 2 Bit 5 S_size 1 Bit 4 S_size 0 Bit 3 F_size 3 Bit 2 F_size 2 Bit 1 F_size 1 Bit 0 F_size 0 Bit definitions: F_size[3:0] = 4h, main Flash size is 2M bit. F_size[3:0] = 5h, main Flash size is 8M bit. S_size[3:0] = 0h, SRAM size is 0K bit. S_size[3:0] = 1h, SRAM size is 16K bit. S_size[3:0] = 3h, SRAM size is 64K bit. Memory_ID1 Register Bit 7 Bit 6 Bit 5 B_type 1 Bit 4 B_type 0 Bit 3 B_size 3 Bit 2 B_size 2 Bit 1 B_size 1 Bit 0 B_size 0 * * *Not used bit should be set to zero. Bit definitions: B_size[3:0] = 0h, Boot block size is 0K bit. B_size[3:0] = 2h, Boot block size is 256K bit. B_type[1:0] = 0h, Boot block is Flash memory. 15 PSD4000 Series Beta Information As shown in Figure 1, the PSD4000 consists of six major types of functional blocks: 9.0 The PSD4000 Functional Blocks Memory Blocks PLD Blocks Bus Interface I/O Ports Power Management Unit JTAG-ISP Interface The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable. 9.1 Memory Blocks The PSD4000 has the following memory blocks: * The main Flash memory * Secondary Flash memory * SRAM. The memory select signals for these blocks originate from the Decode PLD (DPLD) and are user-defined in PSDsoft. Table 7 summarizes which versions of the PSD4000 contain which memory blocks. Table 7. Memory Blocks Main Flash Device PSD4235G2 Secondary Flash Block Size 32KB Flash Size 512KB Sector Size 64KB Sector Size 8KB SRAM 8KB 9.1.1 Main Flash and Secondary Flash Memory Description The main Flash memory block is divided evenly into eight sectors. The secondary Flash memory is divided into four sectors of eight Kbytes each. Each sector of either memory can be separately protected from program and erase operations. Flash memory may be erased on a sector-by-sector basis and programmed word-by-word. Flash sector erasure may be suspended while data is read from other sectors of memory and then resumed after reading. During a program or erase of Flash, the status can be output on the Rdy/Bsy pin of Port PE4. This pin is set up using PSDsoft. 9.1.1.1 Memory Block Selects The decode PLD in the PSD4000 generates the chip selects for all the internal memory blocks (refer to the PLD section). Each of the eight Flash memory sectors have a Flash Select signal (FS0-FS7) which can contain up to three product terms. Each of the four Secondary Flash memory sectors have a Select signal (CSBOOT0-3) which can contain up to three product terms. Having three product terms for each sector select signal allows a given sector to be mapped in different areas of system memory. When using a microcontroller (80C51XA) with separate Program and Data space, these flexible select signals allow dynamic re-mapping of sectors from one space to the other before and after IAP. 9.1.1.2 The Ready/Busy Pin (PE4) Pin PE4 can be used to output the Ready/Busy status of the PSD4000. The output on the pin will be a `0' (Busy) when Flash memory blocks are being written to, or when the Flash memory block is being erased. The output will be a `1' (Ready) when no write or erase operation is in progress. 16 Beta Information PSD4000 Series 9.1.1.3 Memory Operation The main Flash and secondary Flash memories are addressed through the microcontroller interface on the PSD4000 device. The microcontroller can access these memories in one of two ways: The PSD4000 Functional Blocks (cont.) The microcontroller can execute a typical bus write or read operation just as it would if accessing a RAM or ROM device using standard bus cycles. The microcontroller can execute a specific instruction that consists of several write and read operations. This involves writing specific data patterns to special addresses within the Flash to invoke an embedded algorithm. These instructions are summarized in Table 8. Typically, Flash memory can be read by the microcontroller using read operations, just as it would read a ROM device. However, Flash memory can only be erased and programmed with specific instructions. For example, the microcontroller cannot write a single byte directly to Flash memory as one would write a byte to RAM. To program a word into Flash memory, the microcontroller must execute a program instruction sequence, then test the status of the programming event. This status test is achieved by a read operation or polling the Rdy/Busy pin (PE4). The Flash memory can also be read by using special instructions to retrieve particular Flash device information (sector protect status and ID). 9.1.1.3.1 Instructions An instruction is defined as a sequence of specific operations. Each received byte is sequentially decoded by the PSD and not executed as a standard write operation. The instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the time-out value. Some instructions are structured to include read operations after the initial write operations. The sequencing of any instruction must be followed exactly. Any invalid combination of instruction bytes or time-out between two consecutive bytes while addressing Flash memory will reset the device logic into a read array mode (Flash memory reads like a ROM device). The PSD4000 main Flash and secondary Flash support these instructions (see Table 8): Erase memory by chip or sector Suspend or resume sector erase Program a word Reset to read array mode Read Main Flash Identifier value Read sector protection status Bypass Instruction These instructions are detailed in Table 8. For efficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and are followed by a command byte or confirmation byte. The coded cycles consist of writing the data byte AAh to address XAAAh during the first cycle and data byte 55h to address X554h during the second cycle (unless the Bypass Instruction feature is used. See 9.1.1.7). Address lines A15-A12 are don't care during the instruction write cycles. However, the appropriate sector select signal (FSi or CSBOOTi) must be selected. The main Flash and the secondary Flash Block have the same set of instructions (except Read main Flash ID). The chip selects of the Flash memory will determine which Flash will receive and execute the instruction. The main Flash is selected if any one of the FS0-7 is active, and the secondary Flash Block is selected if any one of the CSBOOT0-3 is active. 17 PSD4000 Series Beta Information The PSD4000 Functional Blocks (cont.) Table 8. Instructions Instruction (Note 14) Read (Note 5) Read Main Flash ID (Note 6) Read Sector Protection (Notes 6,8,13) Program a Flash Word Erase One Flash Sector FS0-7 or CSBOOT0-3 Cycle 1 Cycle 2 Cycle 3 1 1 "Read" RA RD AAh 55h 90h @XAAAh @X554h @XAAAh Cycle 4 Cycle5 Cycle 6 Cycle 7 "Read" ID @XX02h 1 AAh 55h 90h "Read" @XAAAh @X554h @XAAAh 00h or 01h @XX04h AAh 55h A0h @XAAAh @X554h @XAAAh AAh 55h 80h @XAAAh @X554h @XAAAh AAh 55h 80h @XAAAh @X554h @XAAAh B0h @xxxh 30h @xxxh F0 @ any address AAh 55h 20h @XAAAh @X554h @XAAAh A0h PD@PA @XXXXh 90h 00h @XXXXh @XXXXh PD@PA AAh @XAAAh AAh @XAAAh 55h @X554h 55h @X554h 30h @SA 10h @XAAAh 30h @next SA (Note 7) 1 1 Erase Flash Block (Bulk Erase) Suspend Sector Erase (Note 11) Resume Sector Erase (Note 12) Reset (Note 6) Unlock Bypass Unlock Bypass Program (Note 9) Unlock Bypass Reset (Note 10) 1 1 1 1 1 1 1 Don't Care. "xxxh" address in the above table must be an even address. Address of the memory location to be read. Data read from location RA during read operation. Address of the memory location to be programmed. Addresses are latched on the falling edge of the WR# (CNTL0) pulse. PA is an even address for PSD in word programming mode. PD = Data (word) to be programmed at location PA. Data is latched on the rising edge of WR# (CNTL0) pulse. SA = Address of the sector to be erased or verified. The chip select (FS0-7 or CSBOOT0-3) of the sector to be erased must be active (high). NOTES: 1. All bus cycles are write bus cycle except the ones with the "read" label. 2. All values are in hexadecimal. 3. FS0-7 and CSBOOT0-3 are active high and are defined in PSDsoft. 4. Only Address bits A11-A0 are used in Instruction decoding. 5. No unlock or command cycles required when device is in read mode. 6. The Reset command is required to return to the read mode after reading the Flash ID, Sector Protect status or if DQ5 (DQ13) goes high. 7. Additional sectors to be erased must be entered within 80s. 8. The data is 00h for an unprotected sector and 01h for a protected sector. In the fourth cycle, the sector chip select is active and (A1 = 1, A0 = 0). 9. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 10. The Unlock Bypass Reset command is required to return to reading array data when the device is in the Unlock Bypass mode. 11. The system may read and program functions in non-erasing sectors, read the Flash ID or read the Sector Protect status, when in the Erase Suspend mode. The erase Suspend command is valid only during a sector erase operation. 12. The Erase Resume command is valid only during the Erase Suspend mode. 13. The MCU cannot invoke these instructions while executing code from the same Flash memory for which the instruction is intended. The MCU must fetch, for example, codes from the Secondary Flash memory when reading the Sector Protection Status of the main Flash. 14. All write bus cycles in an instruction are byte write to even address (XA4Ah or X554h). Flash Programming bys cycle is writing a word to even address. X RA RD PA = = = = 18 Beta Information PSD4000 Series The PSD4000 Functional Blocks (cont.) 9.1.1.4 Power-Up Condition The PSD4000 internal logic is reset upon power-up to the read array mode. The FSi and CSBOOTi select signals, along with the write strobe signal, must be in the false state during power-up for maximum security of the data contents and to remove the possibility of data being written on the first edge of a write strobe signal. Any write cycle initiation is locked when VCC is below VLKO. 9.1.1.5 Read Under typical conditions, the microcontroller may read the Flash, or secondary Flash memories using read operations just as it would a ROM or RAM device. Alternately, the microcontoller may use read operations to obtain status information about a program or erase operation in progress. Lastly, the microcontroller may use instructions to read special data from these memories. The following sections describe these read functions. 9.1.1.5.1 Read the Contents of Memory Main Flash and secodary Flash memories are placed in the read array mode after power-up, chip reset, or a Reset Flash instruction (see Table 8). The microcontroller can read the memory contents of main Flash or secondary Flash by using read operations any time the read operation is not part of an instruction sequence. 9.1.1.5.2 Read the Main Flash Memory Identifier The main Flash memory identifier is read with an instruction composed of 4 operations: 3 specific write operations and a read operation (see Table 8). The PSD4000 main Flash memory ID is E8h. The Secondary Flash does not support this instruction. 9.1.1.5.3 Read the Flash Memory Sector Protection Status The Flash memory sector protection status is read with an instruction composed of 4 operations: 3 specific write operations and a read operation (see Table 8). The read operation will produce 01h if the Flash sector is protected, or 00h if the sector is not protected. The sector protection status for all NVM blocks (main Flash or secondary Flash) can also be read by the microcontroller accessing the Flash Protection and Flash Boot Protection registers in PSD I/O space. See section 9.1.1.9.1 for register definitions. 9.1.1.5.4 Read the Erase/Program Status Bits The PSD4000 provides several status bits to be used by the microcontroller to confirm the completion of an erase or programming instruction of Flash memory. These status bits minimize the time that the microcontroller spends performing these tasks and are defined in Table 9. The status byte resides in even location and can be read as many times as needed. Please note DQ15-8 is even byte for Motorola MCUs with 16 bit data bus. Table 9. Status Bits FSi/ CSBOOTi Flash VIH DQ7 Data Polling DQ6 Toggle Flag DQ5 Error Flag DQ4 X DQ3 Erase Timeout DQ2 X DQ1 X DQ0 X Table 9A. Status Bits for Motorola FSi/ CSBOOTi Flash VIH DQ15 Data Polling DQ14 Toggle Flag DQ13 Error Flag DQ12 X DQ11 Erase Timeout DQ10 X DQ9 X DQ8 X NOTES: 1. X = Not guaranteed value, can be read either 1 or 0. 2. DQ15-DQ0 represent the Data Bus bits, D15-D0. 3. FSi/CSBOOTi are active high. For Flash memory, the microcontroller can perform a read operation to obtain these status bits while an erase or program instruction is being executed by the embedded algorithm. See section 9.1.1.6 for details. 19 PSD4000 Series Beta Information 9.1.1.5.5 Data Polling Flag DQ7 (DQ15 for Motorola) When Erasing or Programming the Flash memory bit DQ7 (DQ15) outputs the complement of the bit being entered for Programming/Writing on DQ7 (DQ15). Once the Program instruction or the Write operation is completed, the true logic value is read on DQ7 (DQ15) (in a Read operation). Flash memory specific features: The PSD4000 Functional Blocks (cont.) Data Polling is effective after the fourth Write pulse (for programming) or after the sixth Write pulse (for Erase). It must be performed at the address being programmed or at an address within the Flash sector being erased. During an Erase instruction, DQ7 (DQ15) outputs a `0'. After completion of the instruction, DQ7 (DQ15) will output the last bit programmed (it is a `1' after erasing). If the location to be programmed is in a protected Flash sector, the instruction is ignored. If all the Flash sectors to be erased are protected, DQ7 (DQ15) will be set to `0' for about 100 s, and then return to the previous addressed location. No erasure will be performed. 9.1.1.5.6 Toggle Flag DQ6 (DQ14 for Motorola) The PSD4000 offers another way for determining when the Flash memory Program instruction is completed. During the internal Write operation and when either the FSi or CSBOOTi is true, the DQ6 (DQ14) will toggle from `0' to `1' and `1' to `0' on subsequent attempts to read any word of the memory. When the internal cycle is complete, the toggling will stop and the data read on the Data Bus is the addressed memory location. The device is now accessible for a new Read or Write operation. The operation is finished when two successive reads yield the same output data. Flash memory specific features: The Toggle bit is effective after the fourth Write pulse (for programming) or after the sixth Write pulse (for Erase). If the location to be programmed belongs to a protected Flash sector, the instruction is ignored. If all the Flash sectors selected for erasure are protected, DQ6 (DQ14) will toggle to `0' for about 100 s and then return to the previous addressed location. 9.1.1.5.7 Error Flag DQ5 (DQ14 for Motorola) During a correct Program or Erase, the Error bit will set to `0'. This bit is set to `1' when there is a failure during Flash programming, Sector erase, or Bulk Erase. In the case of Flash programming, the Error Bit indicates the attempt to program a Flash bit(s) from the programmed state (0) to the erased state (1), which is not a valid operation. The Error bit may also indicate a timeout condition while attempting to program a word. In case of an error in Flash sector erase or word program, the Flash sector in which the error occurred or to which the programmed location belongs must no longer be used. Other Flash sectors may still be used. The Error bit resets after the Reset instruction. A reset instruction is required after detecting the error bit. 9.1.1.5.8 Erase Time-out Flag DQ3 (DQ11 for Motorola) The Erase Timer bit reflects the time-out period allowed between two consecutive Sector Erase instructions. The Erase timer bit is set to `0' after a Sector Erase instruction for a time period of 100 s + 20% unless an additional Sector Erase instruction is decoded. After this time period or when the additional Sector Erase instruction is decoded, DQ3 (DQ11) is set to `1'. A reset instruction is required after detecting the erase timer bit. 20 Beta Information PSD4000 Series The PSD4000 Functional Blocks (cont.) 9.1.1.6 Programming Flash Memory Flash memory must be erased prior to being programmed. The MCU may erase Flash memory all at once or by-sector. Flash memory sector erases to all logic ones, and its bits are programmed to logic zeros. Although erasing Flash memory occurs on a sector or chip basis, programming Flash memory occurs on a word basis. The PSD4000 main Flash and secondary Flash memories require the MCU to send an instruction to program a word or perform an erase function (see Table 8). Once the MCU issues a Flash memory program or erase instruction, it must check for the status of completion. The embedded algorithms that are invoked inside the PSD4000 support several means to provide status to the MCU. Status may be checked using any of three methods: Data Polling, Data Toggle, or the Ready/Busy output pin. 9.1.1.6.1 Data Polling Polling on DQ7 (DQ15) is a method of checking whether a Program or Erase instruction is in progress or has completed. Figure 3 shows the Data Polling algorithm. When the MCU issues a programming instruction, the embedded algorithm within the PSD4000 begins. The MCU then reads the location of the word to be programmed in Flash to check status. Data bit DQ7 (DQ15) of this location becomes the compliment of data bit 7of the original data word to be programmed. The MCU continues to poll this location, comparing DQ7 (DQ15) and monitoring the Error bit on DQ5 (DQ13). When the DQ7 (DQ15) matches data bit 7 of the original data, and the Error bit at DQ5 (DQ13) remains `0', then the embedded algorithm is complete. If the Error bit at DQ5 is `1', the MCU should test DQ7 (DQ15) again since DQ7 (DQ15) may have changed simultaneously with DQ5 (DQ13) (see Figure 3). The Error bit at DQ5 (DQ13) will be set if either an internal timeout occurred while the embedded algorithm attempted to program the location or if the MCU attempted to program a `1' to a bit that was not erased (not erased is logic `0'). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed to compare the word that was written to Flash with the word that was intended to be written. When using the Data Polling method after an erase instruction, Figure 3 still applies. However, DQ7 (DQ15) will be `0' until the erase operation is complete. A `1' on DQ5 (DQ13) will indicate a timeout failure of the erase operation, a `0' indicates no error. The MCU can read any location within the sector being erased to get DQ7 (DQ15) and DQ5 (DQ13) . PSDsoft generates ANSI C code functions which implement these Data Polling algorithms. 21 PSD4000 Series Beta Information The PSD4000 Functional Blocks (cont.) Figure 3. Data Polling Flow Chart START READ DQ5 & DQ7 (DQ13 & DQ15) at VALID EVEN ADDRESS DQ7 (DQ15) = DATA7 (DATA15) YES NO NO DQ5 (DQ13) =1 YES READ DQ7 (DQ15) DQ7 (DQ15) = DATA7 (DATA15) NO FAIL Program/Erase Operation Failed Issue Reset Instruction YES PASS Program/Erase Operation is Completed 9.1.1.6.2 Data Toggle Checking the Data Toggle bit on DQ6 (DQ14) is a method of determining whether a Program or Erase instruction is in progress or has completed. Figure 4 shows the Data Toggle algorithm. When the MCU issues a programming instruction, the embedded algorithm within the PSD4000 begins. The MCU then reads the location to be programmed in Flash to check status. Data bit DQ6 (DQ14) of this location will toggle each time the MCU reads this location until the embedded algorithm is complete. The MCU continues to read this location, checking DQ6 (DQ14) and monitoring the Error bit on DQ5 (DQ13) . When DQ6 (DQ14) stops toggling (two consecutive reads yield the same value), and the Error bit on DQ5 (DQ13) remains `0', then the embedded algorithm is complete. If the Error bit on DQ5 (DQ13) is `1', the MCU should test DQ6 (DQ14) again, since DQ6 (DQ14) may have changed simultaneously with DQ5 (DQ13) (see Figure 4). The Error bit at DQ5 (DQ13) will be set if either an internal timeout occurred while the embedded algorithm attempted to program, or if the MCU attempted to program a `1' to a bit that was not erased (not erased is logic `0'). 22 Beta Information PSD4000 Series 9.1.1.6.2 Data Toggle (cont.) It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed to compare the word that was written to Flash with the word that was intended to be written. When using the Data Toggle method after an erase instructin, Figure 4 still applies. DQ6 (DQ14) will toggle until the erase operation is complete. A `1' on DQ5 (DQ13) will indicate a timeout failure of the erase operation, a `0' indicates no error. The MCU can read any even location within the sector being erased to get DQ6 (DQ14) and DQ5 (DQ13) . PSDsoft generates ANSI C code functions which implement these Data Toggling algorithms. The PSD4000 Functional Blocks (cont.) Figure 4. Data Toggle Flow Chart START READ DQ5 & DQ6 (DQ13 & DQ14) at VALID EVEN ADDRESS DQ6 (DQ14) = TOGGLE NO YES NO DQ5 (DQ13) =1 YES READ DQ6 (DQ14) DQ6 (DQ14) = TOGGLE NO YES FAIL Program/Erase Operation Failed Issue Reset Instruction PASS Program/Erase Operation is Completed 23 PSD4000 Series Beta Information The PSD4000 Functional Blocks (cont.) 9.1.1.7 Unlock Bypass Instruction The unlock bypass feature allows the system to program words to the flash memories faster than using the standard program instruction. The unlock bypass instruction is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h (see Table 8). The flash memory then enters the unlock bypass mode. A two-cycle Unlock Bypass Program instruction is all that is required to program in this mode. The first cycle in this instruction contains the unlock bypass programm command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program instruction, resulting in faster total programming time. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset instructions are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset instruction. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don't care for both cycles. The flash memory then returns to reading array data mode. 9.1.1.8 Erasing Flash Memory 9.1.1.8.1. Flash Bulk Erase Instruction The Flash Bulk Erase instruction uses six write operations followed by a Read operation of the status register, as described in Table 8. If any byte of the Bulk Erase instruction is wrong, the Bulk Erase instruction aborts and the device is reset to the Read Flash memory status. During a Bulk Erase, the memory status may be checked by reading status bits DQ5, DQ6, and DQ7 (DQ13, DQ14, DQ15), as detailed in section 9.1.1.6. The Error bit (returns a `1' if there has been an Erase Failure (maximum number of erase cycles have been executed). It is not necessary to program the array with 00h because the PSD4000 will automatically do this before erasing to 0FFh. During execution of the Bulk Erase instruction, the Flash memory will not accept any instructions. 9.1.1.8.2 Flash Sector Erase Instruction The Sector Erase instruction uses six write operations, as described in Table 8. Additional Flash Sector Erase confirm commands and Flash sector addresses can be written subsequently to erase other Flash sectors in parallel, without further coded cycles, if the additional instruction is transmitted in a shorter time than the timeout period of about 100 s. The input of a new Sector Erase instruction will restart the time-out period. The status of the internal timer can be monitored through the level of DQ3 (DQ11) (Erase time-out bit). If DQ3 (DQ11) is `0', the Sector Erase instruction has been received and the timeout is counting. If DQ3 (DQ11) is `1', the timeout has expired and the PSD4000 is busy erasing the Flash sector(s). Before and during Erase timeout, any instruction other than Erase suspend and Erase Resume will abort the instruction and reset the device to Read Array mode. It is not necessary to program the Flash sector with 00h as the PSD4000 will do this automatically before erasing. During a Sector Erase, the memory status may be checked by reading status bits DQ5, DQ6, and DQ7 (DQ13, DQ14, DQ15), as detailed in section 9.1.1.6. During execution of the erase instruction, the Flash block logic accepts only Reset and Erase Suspend instructions. Erasure of one Flash sector may be suspended, in order to read data from another Flash sector, and then resumed. 24 Beta Information PSD4000 Series 9.1.1.8.3 Flash Erase Suspend Instruction When a Flash Sector Erase operation is in progress, the Erase Suspend instruction will suspend the operation by writing 0B0h to any even address when an appropriate Chip Select (FSi or CSBOOTi) is true. (See Table 8). This allows reading of data from another Flash sector after the Erase operation has been suspended. Erase suspend is accepted only during the Flash Sector Erase instruction execution and defaults to read array mode. An Erase Suspend instruction executed during an Erase timeout will, in addition to suspending the erase, terminate the time out. The Toggle Bit DQ6 stops toggling when the PSD4000 internal logic is suspended. The toggle Bit status must be monitored at an address within the Flash sector being erased. The Toggle Bit will stop toggling between 0.1 s and 15 s after the Erase Suspend instruction has been executed. The PSD4000 will then automatically be set to Read Flash Block Memory Array mode. If an Erase Suspend instruction was executed, the following rules apply: * Attempting to read from a Flash sector that was being erased will output invalid data. * Reading from a Flash sector that was not being erased is valid. * The Flash memory cannot be programmed, and will only respond to Erase Resume and Reset instructions (read is an operation and is OK). * If a Reset instruction is received, data in the Flash sector that was being erased will be invalid. 9.1.1.8.4 Flash Erase Resume Instruction If an Erase Suspend instruction was previously executed, the erase operation may be resumed by this instruction. The Erase Resume instruction consists of writing 030h to any even address while an appropriate Chip Select (FSi or CSBOOTi) is true. (See Table 8.) The PSD4000 Functional Blocks (cont.) 9.1.1.9 Specific Features 9.1.1.9.1 Main Flash and Secondary Flash Sector Protect Each sector of Main Flash and Secondary Flash memory can be separately protected against Program and Erase functions. Sector Protection provides additional data security because it disables all program or erase operations. This mode can be activated (or deactivated) through the JTAG-ISP Port or a Device Programmer. Sector protection can be selected for each sector using the PSDsoft program. This will automatically protect selected sectors when the device is programmed through the JTAG Port or a Device Programmer. Flash sectors can be unprotected to allow updating of their contents using the JTAG Port or a Device Programmer. The microcontroller can read (but cannot change) the sector protection bits. Any attempt to program or erase a protected Flash sector will be ignored by the device. The Verify operation will result in a read of the protected data. This allows a guarantee of the retention of the Protection status. The sector protection status can either be read by the MCU through the Flash protection and secondary Flash protection registers (CSIOP), or use the Read Sector Protection instruction (Table 8). 25 PSD4000 Series Beta Information The PSD4000 Functional Blocks (cont.) Table 10. Sector Protection/Security Bit Definition Flash Protection Register Bit 7 Sec7_Prot Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot Bit Definitions: Sec_Prot Sec_Prot 1 = Main Flash Sector is write protected. 0 = Main Flash Sector is not write protected. Flash Boot Protection Register Bit 7 Security_ Bit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 * * * Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot *: Not used. Bit Definitions: Sec_Prot Sec_Prot Security_Bit 1 = Flash Boot Sector is write protected. 0 = Flash Boot Sector is not write protected. 0 = Security Bit in device has not been set. 1 = Security Bit in device has been set. 9.1.1.9.2 Reset Instruction The Reset instruction consists of one write cycle (see Table 8). It can also be optionally preceded by the standard two write decoding cycles (writing AAh to AAAh and 55h to 554h). The Reset instruction must be executed after: 1. Reading the Flash Protection status or Flash ID 2. When an error condition occurs (DQ5 goes high) during a Flash programming or erase cycle. The Reset instruction will reset the Flash to normal Read Mode immediately. However, if there is an error condition (DQ5 goes high), the Flash memory will return to the Read Mode in 25 Seconds after the Reset instruction is issued. The Reset instruction is ignored when it is issued during a Flash programming or Bulk Erase cycle. The Reset instruction will abort the on going sector erase cycle and return the Flash memory to normal Read Mode in 25 Seconds. 9.1.1.9.3 Reset Pin Input The reset pulse input from the pin will abort any operation in progress and reset the Flash memory to Read Mode. When the reset occurs during a programming or erase cycle, the Flash memory will take up to 25 Seconds to return to Read Mode. It is recommended that the reset pulse (except power on reset, see Reset Section) be at least 25 Seconds such that the Flash memory will always be ready for the MCU to fetch the boot code after reset is over. 26 Beta Information PSD4000 Series The PSD4000 Functional Blocks (cont.) 9.1.2 SRAM The SRAM is enabled when RS0-- the SRAM chip select output from the DPLD-- is high. RS0 can contain up to three product terms, allowing flexible memory mapping. The SRAM can be backed up using an external battery. The external battery should be connected to the Vstby pin (PE6). If you have an external battery connected to the PSD4000, the contents of the SRAM will be retained in the event of a power loss. The contents of the SRAM will be retained so long as the battery voltage remains at 2V or greater. If the supply voltage falls below the battery voltage, an internal power switchover to the battery occurs. Pin PE7 can be configured as an output that indicates when power is being drawn from the external battery. This Vbaton signal will be high with the supply voltage falls below the battery voltage and the battery on PE6 is supplying power to the internal SRAM. The chip select signal (RS0) for the SRAM, Vstby, and Vbaton are all configured using PSDsoft. 9.1.3 Memory Select Signals The main Flash (FSi), secondary Flash (CSBOOTi), and SRAM (RS0) memory select signals are all outputs of the DPLD. They are defined using PSDsoft. The following rules apply to the equations for the internal chip select signals: 1. Main Flash memory and secondary Flash memory sector select signals must not be larger than the physical sector size. 2. Any main Flash memory sector must not be mapped in the same memory space as another Main Flash sector. 3. A secondary Flash memory sector must not be mapped in the same memory space as another Flash Boot sector. 4. SRAM, I/O, and Peripheral I/O spaces must not overlap. 5. A secondary Flash memory sector may overlap a main Flash memory sector. In case of overlap, priority will be given to the Flash Boot sector. 6. SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority will be given to the SRAM, I/O, or Peripheral I/O. Example FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from 8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0 will always access the SRAM. Any address in the range of CSBOOT0 greater than 87FFh (and less than 9FFFh) will automatically address Boot memory segment 0. Any address greater than 9FFFh will access the Flash memory segment 0. You can see that half of the Flash memory segment 0 and one-fourth of Boot segment 0 can not be accessed in this example. Also note that an equation that defined FS1 to anywhere in the range of 8000h to BFFFh would not be valid. Figure 5 shows the priority levels for all memory components. Any component on a higher level can overlap and has priority over any component on a lower level. Components on the same level must not overlap. Level one has the highest priority and level 3 has the lowest. 27 PSD4000 Series Beta Information The PSD4000 Functional Blocks (cont.) Figure 5. Priority Level of Memory and I/O Components Highest Priority Level 1 SRAM, I/O, or Peripheral I/O Level 2 Secondary Flash Memory Level 3 Main Flash Memory Lowest Priority 9.1.3.1. Memory Select Configuration for MCUs with Separate Program and Data Spaces The 80C51XA and compatible family of microcontrollers, can be configured to have separate address spaces for code memory (selected using PSEN) and data memory (selected using RD). Any of the memories within the PSD4000 can reside in either space or both spaces. This is controlled through manipulation of the VM register that resides in the PSD's CSIOP space. The VM register is set using PSDsoft to have an initial value. It can subsequently be changed by the microcontroller so that memory mapping can be changed on-the-fly. For example, you may wish to have SRAM and main Flash in Data Space at boot, and secondary Flash memory in Program Space at boot, and later swap main and secondary Flash memory. This is easily done with the VM register by using PSDsoft to configure it for boot up and having the microcontroller change it when desired. Table 11 describes the VM Register. Table 11. VM Register Bit 7 PIO_EN 0 = disable PIO mode Bit 6* Bit 5* Bit 4 Bit 3 FL_Data Boot_Data 0 = RD can't access Flash 1 = RD access Flash 0 = RD can't access Boot Flash 1 = RD access Boot Flash Bit 2 FL_Code 0 = PSEN can't access Flash Bit 1 Bit 0 Boot_Code SRAM_Code 0 = PSEN can't access Boot Flash 0 = PSEN can't access SRAM 1 = PSEN access SRAM * * 1= enable PIO mode * * 1 = PSEN 1 = PSEN access access Flash Boot Flash NOTE: Bits 6-5 are not used. 28 Beta Information PSD4000 Series 9.1.3.2 Configuration Modes for MCUs with Separate Program and Data Spaces 9.1.3.2.1 Separate Space Modes Code memory space is separated from data memory space. For example, the PSEN signal is used to access the program code from the main Flash Memory, while the RD signal is used to access data from the secondary Flash memory, SRAM and I/O Ports. This configuration requires the VM register to be set to 0Ch. 9.1.3.2.2 . Combined Space Modes The program and data memory spaces are combined into one space that allows the main Flash Memory, secondary Flash memory, and SRAM to be accessed by either PSEN or RD. For example, to configure the main Flash memory in combined space mode, bits 2 and 4 of the VM register are set to "1". 9.1.3.3 80C51XA Memory Map Example See Application Notes for examples. The PSD4000 Functional Blocks (cont.) Figure 6. 80C51XA Memory Modes - Separate Space Mode DPLD RS0 CSBOOT0-3 FS0-7 MAIN FLASH FLASH BOOT BLOCK SRAM CS OE CS OE CS OE PSEN RD Figure 7. 80C51XA Memory Mode - Combined Space Mode DPLD RS0 CSBOOT0-3 FS0-7 MAIN FLASH FLASH BOOT BLOCK SRAM RD CS OE CS OE CS OE VM REG BIT 3 VM REG BIT 4 PSEN VM REG BIT 1 VM REG BIT 2 RD VM REG BIT 0 29 PSD4000 Series Beta Information The PSD4000 Functional Blocks (cont.) 9.1.4 Page Register The eight bit Page Register increases the addressing capability of the microcontroller by a factor of up to 256. The contents of the register can also be read by the microcontroller. The outputs of the Page Register (PGR0-PGR7) are inputs to the PLD decoder and can be included in the Flash Memory, secondary Flash memory, and SRAM chip select equations. If memory paging is not needed, or if not all 8 page register bits are needed for memory paging, then these bits may be used in the CPLD for general logic. See Application Notes. Figure 8 shows the Page Register. The eight flip flops in the register are connected to the internal data bus. The microcontroller can write to or read from the Page Register. The Page Register can be accessed at address location CSIOP + E0h. Figure 8. Page Register RESET D0 D1 DATA BUS D2 D3 D4 D5 D6 R/W D7 Q0 Q1 Q2 Q3 Q4 Q5 PGR0 PGR1 PGR2 PGR3 PGR4 PGR5 PGR6 DPLD AND GPLD INTERNAL SELECTS AND LOGIC Q6 PGR7 Q7 PAGE REGISTER FLASH PLD 30 Beta Information PSD4000 Series The PSD4000 Functional Blocks (cont.) 9.1.5 Memory ID Registers The 8-bit read only memory status registers are included in the CSIOP space. The user can determine the memory configuration of the PSD device by reading the Memory ID0 and Memory ID1 registers. The content of the registers are defined as follow: Memory_ID0 Register Bit 7 S_size 3 Bit 6 S_size 2 Bit 5 S_size 1 Bit 4 S_size 0 Bit 3 F_size 3 Bit 2 F_size 2 Bit 1 F_size 1 Bit 0 F_size 0 Bit Definition F_size3 0 0 0 0 0 0 0 F_size2 0 0 0 0 1 1 1 F_size1 0 0 1 1 0 0 1 F_size0 0 1 0 1 0 1 0 Main Flash Size (Bit) none 256K 512K 1M 2M 4M 8M SRAM Size (Bit) none 16K 32K 64K S_size3 0 0 0 0 Memory_ID1 Register Bit 7 Bit 6 S_size2 0 0 0 0 S_size1 0 0 1 1 S_size0 0 1 0 1 Bit 5 B_type 1 Bit 4 B_type 0 Bit 3 B_size 3 Bit 2 B_size 2 Bit 1 B_size 1 Bit 0 B_size 0 * Bit Definition B_size3 0 0 0 0 B_type1 0 0 * *Not used bit should be set to zero. B_size2 0 0 0 0 B_type0 0 1 B_size1 0 0 1 1 Boot Block Type Flash EEPROM B_size0 0 1 0 1 Boot Block Size (Bit) none 128K 256K 512K 31 PSD4000 Series Beta Information The PSD4000 Functional Blocks (cont.) 9.2 PLDs The PLDs bring programmable logic functionality to the PSD4000. After specifying the logic for the PLDs in PSDsoft, the logic is programmed into the device and available upon power-up. The PSD4000 contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD). The PLDs are briefly discussed in the next few paragraphs, and in more detail in sections 9.2.1 and 9.2.2. Figure 10 shows the configuration of the PLDs. The DPLD performs address decoding for internal components, such as memory, registers, and I/O port selects. The CPLD can be used for logic functions, such as loadable counters and shift registers, state machines, and encoding and decoding logic. These logic functions can be constructed using the 16 Output MicroCells (OMCs), 24 Input MicroCells (IMCs), and the AND array. The CPLD can also be used to generate external chip selects. The AND array is used to form product terms. These product terms are specified using PSDsoft. An Input Bus consisting of 82 signals is connected to the PLDs. The signals are shown in Table 12. Table 12. DPLD and CPLD Inputs Input Source MCU Address Bus MCU Control Signals Reset Power Down Port A Input MicroCells Port B Input MicroCells Port C Input MicroCells Port D Inputs Port F Inputs Page Register MicroCell A Feedback MicroCell B Feedback Flash Programming Status Bit NOTE: The address inputs are A[19:4] in 80C51XA mode. Input Name A[15:0]* CNTL[2:0] RST PDN PA[7-0] PB[7-0] PC[7-0] PD[3:0] PF[7:0] PGR(7:0) MCELLA.FB[7:0] MCELLB.FB[7:0] Rdy/Bsy Number of Signals 16 3 1 1 8 8 8 4 8 8 8 8 1 The Turbo Bit The PLDs in the PSD4000 can minimize power consumption by switching to standby when inputs remain unchanged for an extended time of about 70 ns. Setting the Turbo mode bit to off (Bit 3 of the PMMR0 register) automatically places the PLDs into standby if no inputs are changing. Turbo-off mode increases propagation delays while reducing power consumption. Refer to the Power Management Unit section on how to set the Turbo Bit. Additionally, five bits are available in the PMMR2 register to block MCU control signals from entering the PLDs. This reduces power consumption and can be used only when these MCU control signals are not used in PLD logic equations. 32 Beta Information 8 DATA BUS PAGE REGISTER DECODE PLD FLASH MEMORY SELECTS FLASH BOOT MEMORY SELECTS SRAM SELECT CSIOP SELECT PERIPHERAL I/O MODE SELECTS JTAG SELECT 82 4 1 1 2 1 Figure 9. PLD Block Diagram 8 PLD INPUT BUS 16 OUTPUT MICROCELL FEEDBACK DIRECT MICRO CELL ACCESS FROM MCU DATA BUS CPLD 16 OUTPUT MICROCELL PT ALLOC. 82 MCELLA TO PORT A MCELLB TO PORT B I/O PORTS 8 24 INPUT MICROCELL (PORT A,B,C) 8 8 EXTERNAL CHIP SELECTS TO PORT C OR F DIRECT MICROCELL INPUT TO MCU DATA BUS 24 INPUT MICROCELL & INPUT PORTS 12 PORT D AND F INPUTS PSD4000 Series 33 PSD4000 Series Beta Information Each of the two PLDs has unique characteristics suited for its applications They are described in the following sections. 9.2.1 Decode PLD (DPLD) The DPLD, shown in Figure 10, is used for decoding the address for internal and external components. The DPLD can generate the following decode signals: * 8 sector selects for the main Flash memory (three product terms each) * 4 sector selects for the Flash Boot memory (three product terms each) * 1 internal SRAM select signal (three product terms) * 1 internal CSIOP (PSD configuration register) select signal * 1 JTAG select signal (enables JTAG-ISP on Port E) * 2 internal peripheral select signals (peripheral I/O mode). 9.2.2 Complex PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift registers, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate 8 external chip selects, routed to Port C or F. Although external chip selects can be produced by any Output MicroCell, these eight external chip selects on Port C or F do not consume any Output MicroCells. As shown in Figure 9, the CPLD has the following blocks: * 24 Input MicroCells (IMCs) * 16 Output MicroCells (OMCs) * Product Term Allocator * AND array capable of generating up to 196 product terms * Four I/O ports. Each of the blocks are described in the subsections that follow. The Input and Output MicroCells are connected to the PSD4000 internal data bus and can be directly accessed by the microcontroller. This enables the MCU software to load data into the Output MicroCells or read data from both the Input and Output MicroCells. This feature allows efficient implementation of system logic and eliminates the need to connect the data bus to the AND logic array as required in most standard PLD macrocell architectures. The PSD4000 Functional Blocks (cont.) 34 Beta Information 3 3 3 3 (INPUTS) 3 FS0 3 (8) 3 (8) 3 (8) 3 (16) 3 (4) 3 (1) 3 (3) (1) 3 (1) CSIOP PSEL0 PSEL1 JTAGSEL PERIPHERAL I/O MODE SELECT RS0 SRAM SELECT I/O DECODER SELECT FS7 8 FLASH MEMORY SECTOR SELECTS (32) CSBOOT 3 CSBOOT 2 CSBOOT 1 4 SECONDARY FLASH MEMORY SECTOR SELECTS Figure 10. DPLD Logic Array CSBOOT 0 I /O PORTS (PORT A,B,C,F) MCELLA.FB [7:0] (FEEDBACKS) MCELLB.FB [7:0] (FEEDBACKS) PGR0 - PGR7 A[15:0] * PD[3:0] (ALE,CLKIN,CSI) PDN (APD OUTPUT) CNTRL[2:0] (READ/WRITE CONTROL SIGNALS) RESET RD_BSY *NOTE: 1. The address inputs are A[19:4] in 80C51XA mode. 2. Additional address lines can be brought into PSD via Port A, B, C, D or F. PSD4000 Series 35 PLD INPUT BUS AND ARRAY PR DI LD D/T Q COMB. /REG SELECT PDR INPUT MUX D/T/JK FF SELECT CK CL WR PT CLEAR D Q DIR REG. PT CLOCK GLOBAL CLOCK CLOCK SELECT SELECT PLD INPUT BUS PT OUTPUT ENABLE (OE) MICRO CELL FEEDBACK I/O PORT INPUT MUX PT INPUT LATCH GATE/CLOCK MUX ALE/AS MUX 36 MCU ADDRESS / DATA BUS PSD4000 Series PRODUCT TERMS FROM OTHER MICRO CELLS CPLD MICROCELLS I/O PORTS MCU DATA IN MCU LOAD D Q MUX WR UP TO 10 PRODUCT TERMS MICRO CELL OUT TO MCU PLD OUTPUT DATA DATA LOAD CONTROL LATCHED ADDRESS OUT PT PRESET PRODUCT TERM ALLOCATOR Figure 11. The MicroCell and I/O Port I/O PIN POLARITY SELECT INPUT MICROCELLS QD QD G Beta Information Beta Information PSD4000 Series 9.2.2.1 Output MicroCell Eight of the Output MicroCells are connected to Port A pins are named as McellA0-7. The other eight MicroCells are connected to Port B pins are named as McellB0-7. The PSD4000 Functional Blocks (cont.) Table 13. Output MicroCell Port and Data Bit Assignments Native Product Terms 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 Maximum Borrowed Product Terms 6 6 6 6 6 6 6 6 5 5 5 5 6 6 6 6 Data Bit for Loading or Reading D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Motorola 16-Bit MCU for Loading or Reading D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 Output MicroCell McellA0 McellA1 McellA2 McellA3 McellA4 McellA5 McellA6 McellA7 McellB0 McellB1 McellB2 McellB3 McellB4 McellB5 McellB6 McellB7 Port Assignment Port A0 Port A1 Port A2 Port A3 Port A4 Port A5 Port A6 Port A7 Port B0 Port B1 Port B2 Port B3 Port B4 Port B5 Port B6 Port B7 The Output MicroCell (OMC) architecture is shown in Figure 12. As shown in the figure, there are native product terms available from the AND array, and borrowed product terms available (if unused) from other OMCs. The polarity of the product term is controlled by the XOR gate. The OMC can implement either sequential logic, using the flip-flop element, or combinatorial logic. The multiplexer selects between the sequential or combinatorial logic outputs. The multiplexer output can drive a Port pin and has a feedback path to the AND array inputs. The flip-flop in the OMC can be configured as a D, T, JK, or SR type in the PSDsoft program. The flip-flop's clock, preset, and clear inputs may be driven from a product term of the AND array. Alternatively, the external CLKIN signal can be used for the clock input to the flip-flop. The flip-flop is clocked on the rising edge of the clock input. The preset and clear are active-high inputs. Each clear input can use up to two product terms. 37 PSD4000 Series Beta Information 9.2.2.2 The Product Term Allocator The CPLD has a Product Term Allocator. The PSDsoft uses the Allocator to borrow and place product terms from one MicroCell to another. The following list summarizes how product terms are allocated: * McellA0-7 all have three native product terms and may borrow up to six more * McellB0-3 all have four native product terms and may borrow up to five more * McellB4-7 all have four native product terms and may borrow up to six more. Each MicroCell may only borrow product terms from certain other MicroCells. Product terms already in use by one MicroCell will not be available for a different MicroCell. If an equation requires more product terms than what is available to it, then "external" product terms will be required, which will consume other OMCs. If external product terms are used, extra delay will be added for the equation that required the extra product terms. This is called product term expansion. PSDsoft will perform this expansion as needed. 9.2.2.3 Loading and Reading the Output MicroCells (OMCs) The OMCs occupy a memory location in the MCU address space, as defined by the CSIOP (refer to the I/O section). The flip-flops in each of the 16 OMCs can be loaded from the data bus by a microcontroller. Loading the OMCs with data from the MCU takes priority over internal functions. As such, the preset, clear, and clock inputs to the flip-flop can be overridden by the MCU. The ability to load the flip-flops and read them back is useful in such applications as loadable counters and shift registers, mailboxes, and handshaking protocols. Data is loaded to the OMCs on the trailing edge of the WR signal . 9.2.2.4 The OMC Mask Register There is one Mask Register for each of the two groups of eight OMCs. The Mask Registers can be used to block the loading of data to individual OMCs. The default value for the Mask Registers is 00h, which allows loading of the OMCs. When a given bit in a Mask Register is set to a `1', the MCU will be blocked from writing to the associated OMC. For example, suppose McellA0-3 are being used for a state machine. You would not want a MCU write to McellA to overwrite the state machine registers. Therefore, you would want to load the Mask Register for McellA (Mask MicroCell A) with the value 0Fh. 9.2.2.5 The Output Enable of the OMC The OMC can be connected to an I/O port pin as a PLD output. The output enable of each Port pin driver is controlled by a single product term from the AND array, ORed with the Direction Register output. The pin is enabled upon power up if no output enable equation is defined and if the pin is declared as a PLD output in PSDsoft. If the OMC output is declared as an internal node and not as a Port pin output in the PSDabel file, then the Port pin can be used for other I/O functions. The internal node feedback can be routed as an input to the AND array. The PSD4000 Functional Blocks (cont.) 38 Beta Information (cont.) The PSD4000 Functional Blocks MASK REG. MICROCELL CS INTERNAL DATA BUS RD PT ALLOCATOR ENABLE (.OE) PRESET(.PR) PT PT DIN PR MUX PT POLARITY SELECT IN CLR PROGRAMMABLE FF (D/T/JK /SR) MUX CLEAR (.RE) PT CLK CLKIN LD Q COMB/REG SELECT WR DIRECTION REGISTER Figure 12. CPLD Output MicroCell AND ARRAY I/O PIN PLD INPUT BUS PORT DRIVER FEEDBACK (.FB) PORT INPUT INPUT MICROCELL PSD4000 Series 39 PSD4000 Series Beta Information 9.2.2.6 Input MicroCells (IMCs) The CPLD has 24 IMCs, one for each pin on Ports A, B, and C. The architecture of the IMC is shown in Figure 13. The IMCs are individually configurable, and can be used as a latch, register, or to pass incoming Port signals prior to driving them onto the PLD input bus. The outputs of the IMCs can be read by the microcontroller through the internal data bus. The enable for the latch and clock for the register are driven by a multiplexer whose inputs are a product term from the CPLD AND array or the MCU address strobe (ALE/AS). Each product term output is used to latch or clock four IMCs. Port inputs 3-0 can be controlled by one product term and 7-4 by another. Configurations for the IMCs are specified by PSDsoft. Outputs of the IMCs can be read by the MCU via the IMC buffer. See the I/O Port section on how to read the IMCs. IMCs can use the address strobe to latch address bits higher than A15. Any latched addresses are routed to the PLDs as inputs. IMCs are particularly useful with handshaking communication applications where two processors pass data back and forth through a common mailbox. Figure 14 shows a typical configuration where the Master MCU writes to the Port A Data Out Register. This, in turn, can be read by the Slave MCU via the activation of the "Slave-Read" output enable product term. The Slave can also write to the Port A IMCs and the Master can then read the IMCs directly. Note that the "Slave-Read" and "Slave-Wr" signals are product terms that are derived from the Slave MCU inputs RD, WR, and Slave_CS. The PSD4000 Functional Blocks (cont.) Figure 13. Input MicroCell INTERNAL DATA BUS INPUT MICROCELL _ RD ENABLE ( .OE ) OUTPUT MICROCELLS A AND MICROCELL B DIRECTION REGISTER PT AND ARRAY PLD INPUT BUS I/O PIN PT PORT DRIVER MUX Q D MUX PT ALE/AS D FF FEEDBACK Q D G LATCH INPUT MICROCELL 40 Beta Information PSD4000 Series The PSD4000 Functional Blocks (cont.) Figure 14. Handshaking Communication Using Input MicroCells PSD4235 SLAVE- CS RD WR SLAVE-READ PORT A DATA OUT REGISTER MCU-RD MASTER MCU MCU-WR CPLD MCU-WR D [ 7:0] D Q PORT A SLAVE MCU SLAVE-WR D [ 7:0] PORT A INPUT MICRO CELL Q MCU-RD D 9.2.2.7 External Chip Select The CPLD also provides eight chip select outputs that can be used to select external devices. The chip selects can be routed to either Port C or Port F, depending on the pin declaration in the PSDsoft. Each chip select (ECS0-7) consists of one product term that can be configured active high or low. The output enable of the pin is controlled by either the output enable product term or the Direction Register. (See Figure 15). Figure 15. External Chip Select ENABLE (.OE) PT DIRECTION REGISTER PLD INPUT BUS CPLD AND ARRAY ECS PT ECS TO PORT C OR F PORT PIN POLARITY BIT PORT C OR PORT F 41 PSD4000 Series Beta Information The PSD4000 Functional Blocks (cont.) 9.3 Microcontroller Bus Interface The "no-glue logic" PSD4000 Microcontroller Bus Interface can be directly connected to most popular microcontrollers and their control signals. Key 16-bit microcontrollers with their bus types and control signals are shown in Table 14. The MCU interface type is specified using the PSDsoft. Table 14. Microcontrollers and their Control Signals MCU 68302, 68306 MMC2001 68330, 68331 68332, 68340 68LC302, MMC2001 68HC16 68HC912 68HC812*** 80196 80196SP 80186 80C161 80C164-80C167 80C51XA H8/3044 M37702M2 CNTL0 R/W R/W WEL R/W R/W R/W WR WRL WR WR WRL WRL R/W CNTL1 LDS DS OE DS E E RD RD RD RD RD RD E SIZ0 LSTRB LSTRB BHE CNTL2 UDS SIZ0 PD3 PD0** AS AS AS AS E ADIO0 - A0 - A0 A0 A0 A0 A0 A0 A0 A4/D0 A0 A0 PF3-PF0 * * WEH * * * * * * * * * * A3-A1 - * DBE * * WRH * ALE ALE ALE ALE ALE AS ALE * BHE BHE PSEN * * WRH WRH * BHE * * ***Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PD3-0, PF3-0) can be ***configured for other I/O functions. ***ALE/AS input is optional for microcontrollers with a non-multiplexed bus. ***This configuration is for 68C812A4_EC at 5MHz, 3V only. only. 9.3.1. PSD4000 Interface to a Multiplexed Bus Figure 16 shows an example of a system using a microcontroller with a 16-bit multiplexed bus and a PSD4000. The ADIO port on the PSD4000 is connected directly to the microcontroller address/data bus. ALE latches the address lines internally. Latched addresses can be brought out to Port E, F or G. The PSD4000 drives the ADIO data bus only when one of its internal resources is accessed and the RD input is active. Should the system address bus exceed sixteen bits, Ports A, B, C, or F may be used as additional address inputs. 9.3.2. PSD4000 Interface to a Non-Multiplexed Bus Figure 17 shows an example of a system using a microcontroller with a 16-bit non-multiplexed bus and a PSD4000. The address bus is connected to the ADIO Port, and the data bus is connected to Port F and G. Port F and G are in tri-state mode when the PSD4000 is not accessed by the microcontroller. Should the system address bus exceed sixteen bits, Ports A, B or C may be used for additional address inputs. 42 Beta Information PSD4000 Series The PSD4000 Functional Blocks (cont.) Figure 16. An Example of a Typical 16-Bit Multiplexed Bus Interface PSD4235G2 MICROCONTROLLER AD[ 7:0] ADIO PORT PORT F A [ 7: 0] (OPTIONAL) AD[ 15:8] PORT G WR RD BHE WR (CNTRL0) RD (CNTRL1) BHE (CNTRL2) RST ALE ALE (PD0) PORT D RESET PORT A,B, or C A [ 15: 8] (OPTIONAL) A [ 23:16] (OPTIONAL) Figure 17. An Example of a Typical 16-Bit Non-Multiplexed Bus Interface PSD4235G2 D [ 15:0] MICROCONTROLLER A [ 15:0] ADIO PORT PORT F D [ 7:0] PORT G WR RD BHE WR (CNTRL0) RD (CNTRL1) BHE (CNTRL2) RST PORT A,B or C D[ 15:8] (OPTIONAL) A[ 23:16] (OPTIONAL) ALE ALE (PD0) PORT D RESET 43 PSD4000 Series Beta Information 9.3.3 Data Byte Enable Reference Microcontrollers have different data byte orientations. The following tables show how the PSD4235G2 interprets byte/word operation in different bus write configurations. Even-byte refers to locations with address A0 equal to zero and odd byte as locations with A0 equal to one. 9.3.4 Microcontroller Interface Examples Figures 18 through 21 show examples of the basic connections between the PSD4235G2 and some popular microcontrollers. The PSD4235G2 Control input pins are labeled as the microcontroller function for which they are configured. The MCU interface is specified using PSDsoft. The PE6 pin should be grounded if Vstby is not used. 9.3.4.1 80C196 and 80C186 In Figure 18, the Intel 80C196 microcontroller, which has a multiplexed sixteen-bit bus, is shown connected to a PSD4235G2. The WR and RD signals are connected to the CNTL0-1 pins. The BHE signal is used for high data byte selection. If BHE is not used, the PSD can be configured to receive the WRL and WRH from the MCU. Higher address inputs (A16-A19) can be routed to Port A, B or C as inputs to the PLD. The AMD 80186 family has the same bus connection to the PSD as the 80C196. The PSD4000 Functional Blocks (cont.) Table 15. 16-Bit Data Bus with BHE BHE 0 0 1 A0 0 1 0 D15-D8 Odd Byte Odd Byte - D7-D0 Even Byte - Even Byte Table 16. 16-Bit Data Bus with WRH and WRL WRH 0 0 1 WRL 0 1 0 D15-D8 Odd Byte Odd Byte - D7-D0 Even Byte - Even Byte Table 17. 16-Bit Data Bus with SIZ0, A0 (Motorola MCU) SIZ0 0 1 1 A0 0 0 1 D15-D8 Even Byte Even Byte - D7-D0 Odd Byte - Odd Byte Table 18. 16-Bit Data Bus with UDS, LDS (Motorola MCU) LDS 0 1 0 UDS 0 0 1 D15-D8 Even Byte Even Byte - D7-D0 Odd Byte - Odd Byte 44 Beta Information PSD4000 Series 9.3.4.2 MC683XX and 68HC16 Figure 19 shows a Motorola MC68331 with non-multiplexed sixteen-bit data bus and 24-bit address bus. The data bus from the MC68331 is connected to Port F (D0-7) and Port G (D8-D15). The SIZ0 and A0 inputs determine the high/low byte selection. The R/W, DS and SIZ0 are connected to the CNTL0-2 pins. The 68HC16 and other members of the 683XX family have the same connection as the 68331 shown in Figure 19. 9.3.4.3 80C51XA The Philips 80C51XA microcontroller has a 16-bit multiplexed bus with burst cycles. Address bits A[3:1] are not multiplexed while A[19:4] are multiplexed with data bits D[15:0]. The PSD4235G2 supports the 80C51XA burst mode. The WRH signal is connected to the PD3 and the WRL is connected to CNTL0 pin. The RD and PSEN signal is connected to CNTL1-2 pins. Figure 19 shows the XA schematic. The 80C51XA improves bus throughput and performance by issuing Burst cycles to fetch codes from memory. In Burst cycles, addresses A19-4 are latched internally by the PSD, while the 80C51XA drives the A3-1 lines to sequentially fetch up to 16 bytes of code. The PSD access time is then measured from address A3-A1 valid to data in valid. The PSD bus timing requirement in Burst cycle is identical to the normal bus cycle except the address set up or hold time with respect to ALE is not required. 9.3.4.4 H8/300 Figure 20 shows a Hitachi H8/2350 with non-multiplexed sixteen-bit data bus and 24-bit address bus. The H8 data bus is connected to Port F (D0-7) and Port G (D8-15). The WRL, WRH and RD signals are connected to the CNTL0, PD3 and CNTL1 pins respectively. The AS connection is optional and is required if the address are to be latched. 9.3.4.5 MMC2001 The Motorola MCORE MMC2001 microcontroller has a MOD input pin that selects internal or external boot ROM. The PSD4000 can be configured as the external flash boot ROM or as extension to the internal ROM. The MMC2001 has a 16-bit external data bus and 20 address lines with external Chip Select signals. The Chip Select Control Registers allow the user to customize the bus interface and timing to fit the individual system requirement. A typical interface configuration to the PSD4000 is shown in Figure 22. The MMC2001's R/W signal is connected to the cntl0 pin, while EB0 and EB1 (enable byte0 and byte1) are connected to the cntl1 (UDS) and cntl2 (LDS) pins. The WEN bit in the Chip Select Control Register should set to 1 to terminate the EB[0:1] earlier to provide the write data hold time for the PSD. The WSC and WWS bits in the Control Register are set to wait states that meet the PSD access time requirement. Another option is to configure the EB0 and EB1 as WRL and WRH signals. In this case the PSD4000 control setting will be: OE, WRL, WRH where OE is the read signal from the MMC2001. 9.3.4.6 C16X Family The PSD4000 supports Infineon's C16X family of microcontrollers (C161-C167) in both the multiplexed and non-multiplexed bus configuration. In Figure 23 the C167CR is shown connected to the PSD4000 in a multiplexed bus configuration. The control signals from the MCU are WR, RD, BHE and ALE and are routed to the corresponding PSD pins. The C167 has another control signal setting (RD, WRL, WRH, ALE) which is also supported by the PSD4000. The PSD4000 Functional Blocks (cont.) 45 46 A[19:16] A[19:16] AD[15:0] AD[15:0] VCC PSD4000 Series 80C196NT PSD4235G2 9 VCC VCC VCC 29 69 67 X1 U3 CRYATAL 66 X2 32 NMI P3.0/AD0 P3.1/AD1 P3.2/AD2 P3.3/AD3 P3.4/AD4 P3.5/AD5 P3.6/AD6 P3.7/AD7 P4.0/AD8 P4.1/AD9 P4.2/AD10 P4.3/AD11 P4.4/AD12 P4.5/AD13 P4.6/AD14 P4.7/AD15 ADIO8 ADI09 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 22 21 20 19 18 17 16 15 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 13 14 15 16 17 18 19 20 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 21 22 23 24 25 26 27 28 30 29 28 27 26 25 24 23 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 3 4 5 6 7 10 11 12 ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 31 32 33 34 35 36 37 38 58 59 60 61 P6.0/EPA8 P6.1EPA9 P6.2/T1CLK P6.3/T1DIR 44 45 46 47 A16 A17 A18 A19 WR 59 60 CRTL0 (WR) CNTL1 (RD) CNTL2 (BHE) 40 RD BHE EP.0/A16 EP.1/A17 EP.2/A18 EP.3/A19 WR/WRL/P5.2 RD/P5.3 BHE/WRH/P5.5 4 ALE 8 79 80 1 2 14 13 12 11 9 7 Figure 18. Interfacing the PSD4235G2 with an 80C196 ACH4/P0.4/PMD.0 ACH5/P0.5/PMD.1 ACH6/P0.6/PMD.2 ACH7/P0.7/PMD.3 36 37 38 39 40 41 42 43 ALE/ADV/P5.0 31 RESET 39 PDO (ALE) PD1 (CLKIN) PD2 (CSI) PD3 (WRH) P2.0/TX/PVR P2.1/RXD/PALE P2.2/EXINT/PROG P2.3/INTB P2.4/INTINTOUT P2.5/HLD P2.6/HLDA/CPVER P2.7/CLKOUT/PAC PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 51 52 53 54 55 56 57 58 62 63 54 65 RESET P6.4/SC0 P6.5/6D0 P6.6/SC1 P6.7/SD1 RESET 49 6 48 READY/P5.6 EA VCC BUSWIDTH/P5.7 INST/P5.1 SLPINT/P5.4 1 10 3 33 2 VREF VPP ANGND PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 71 72 73 74 75 76 77 78 PEO (TMS) PE1 (TCK/ST) PE2 (TDI) PD2 (TDO) PE4 (TSTAT/RDY) PE5 (TERR) PE6 (VSTBY) PE7 (VBATON) PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 GND GND GND GND GND 8 30 49 50 70 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 A16 A17 A18 A19 50 57 56 55 54 53 52 51 P1.7/EPA7 P1.0/EPAQ/T2CLK P1.1/EPA1 P1.2/EPA2/T2DIR P1.3/EPA3 P1.4/EPA4 P1.5/EPA5 P1.6/EPA6 Beta Information RESET D[15:0] D[15:0] A[23:0] VCC A[23:0] Beta Information MC68331 PSD4235G2 9 VCC VCC VCC PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 21 22 23 24 25 26 27 28 31 32 33 34 35 36 37 38 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 29 69 A0 A1 A2 A3 A4 A5 A6 A7 ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 A8 A9 A10 A11 A12 A13 A14 A15 13 14 15 16 17 18 19 20 90 20 21 22 23 24 25 26 A0 A1 A2 A3 A4 A5 A6 A7 3 4 5 6 7 10 11 12 D0 D1 D2 D3 D4 D5 D6 D7 111 110 109 108 105 104 103 102 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 100 99 98 97 94 93 92 91 D8 D9 D10 D11 D12 D13 D14 D15 Figure 19. Interfacing the PSD4235G2 with an MC68331 A16 A17 A18 A19 A20 A21 A22 A23 R/W 59 60 SIZ0 40 DS AS CRTL0 (R/W) CNTL1 (DS) CNTL2 (SIZ0) 89 88 SIZ0 AS RESET 68 RESET 82 81 DSACK0 DSACK1 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19_CS6 A20_CS7 A21_CS8 A22_CS9 A23_CS10 R_W DS 79 80 1 2 39 PD0 (AS) PD1 (CLKIN) PD2 (CSI) PD3 RESET 27 30 31 32 33 35 36 37 38 41 42 121 122 123 124 125 79 85 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 77 76 75 74 73 72 71 SIZ1 CLKOUT 66 80 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 71 72 73 74 75 76 77 78 PE0 (TMS) PE1 (TCK/ST) PE2 (TDI) PD3 (TDO) PE4 (TSTAT/RDY) PE5 (TERR) PE6 (VSTBY) PE7 (VBATON) GND GND GND GND GND 8 30 49 50 70 CSBOOT BR_CSO BG_CS1 BGACK_CS2 FCO_CS3 FC1_CS4 FC2_CS5 112 113 114 115 118 119 120 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 41 42 43 44 45 46 47 48 A16 A17 A18 A19 RESET RESET PSD4000 Series 47 48 D[15:0] D[15:0] A[3:1] A[3:1] VCC PSD4000 Series XA-G3 21 XTAL1 A1 A2 A3 VCC VCC VCC PSD4235G2 9 29 69 CRYATAL 20 XTAL2 11 RXD0 13 TXD0 6 RXD1 7 TXD1 9 T2EX 8 T2 10 T0 A12D8 A13D9 A14D10 A15D11 A16D12 A17D13 A18D14 A19D15 ADIO8 ADI09 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 24 25 26 27 28 29 30 31 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 A12D8 A13D9 A14D10 A15D11 A16D12 A17D13 A18D14 A19D15 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7 43 42 41 40 39 38 37 36 ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7 3 4 5 6 7 10 11 12 31 32 33 34 35 36 37 38 RESET 10 14 15 RST INT0 INT1 WRL 59 60 CRTL0 (WR) CNTL1 (RD) CNTL2 40 EA/WAIT BUSW PSEN 33 WRH 39 RESET ALE 32 PSEN 79 80 1 2 2 18 19 RD 35 Figure 20. Interfacing the PSD4235G2 with a 80C51XA-G3 VCC A3 A2 A1 A0/WRH WRL RD 5 4 3 A3 A2 A1 17 ALE PD0 (ALE) PD1 (CLKIN) PD2 (CSI) PD3 (WRH) PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 RESET 71 72 73 74 75 76 77 78 PEO (TMS) PE1 (TCK/ST) PE2 (TDI) PD3 (TDO) PE4 (TSTAT/RDY) PE5 (TERR) PE6 (VSTBY) PE7 (VBATON) GND GND GND GND GND 8 30 49 50 70 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 41 42 43 44 45 46 47 48 Beta Information D[15:0] A[23:0] A[23:0] VCC D[15:0] Beta Information H85/2350 9 VCC VCC VCC ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 21 22 23 24 25 26 27 28 D8 D9 D10 D11 D12 D13 D14 D15 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 31 32 33 34 35 36 37 38 D0 D1 D2 D3 D4 D5 D6 D7 29 69 34 35 36 37 39 40 41 42 PE0/D0 PE0/D1 PE0/D2 PE0/D3 PE0/D4 PE0/D5 PE0/D6 PE0/D7 PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 A8 A9 A10 A11 A12 A13 A14 A15 13 14 15 16 17 18 19 20 PD0/D8 PD1/D9 PD2/D10 PD3/D11 PD4/D12 PD5/D13 PD6/D14 PD7/D15 A0 A1 A2 A3 A4 A5 A6 A7 3 4 5 6 7 10 11 12 43 44 45 46 48 49 50 51 2 3 4 5 7 8 9 10 PSD4235G2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 78 EXTAL WRL 59 60 CRTL0 (WRL) CNTL1 (RD) CNTL2 40 RD AS WRH RESET 39 79 80 1 2 U3 CRYATAL 77 XTAL PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17 PA2/A18 PB3/A19 PA4/A20/IRQ4 PA5/A21/IRQ5 PA6/A22/IRQ6 PA7/A23/1RQ7 LWR RD A16 A17 A18 A19 A20 A21 A22 A23 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 51 52 53 54 55 56 57 58 AS HWR RESET WDTOVF STBY 112 111 110 109 108 107 106 105 95 96 97 98 99 100 101 102 92 AN0 AN1 AN2 AN3 AN4 AN5 AN6/DA0 AN7/DA1 ADTRG PG0/CAS/OE PG1/CS3 PG2/CS2 PG3/CS1 PG4/CS0 116 117 118 119 120 75 72 71 72 73 74 75 76 77 78 PE0 (TMS) PE1 (TCK/ST) PE2 (TDI) PD3 (TDO) PE4 (TSTAT/RDY) PE5 (TERR) PE6 (VSTBY) PE7 (VBATON) GND GND GND GND GND 8 30 49 50 70 73 84 82 PD0 (AS) PD1 (CLKIN) PD2 (CSI) PD3 (WRH) Figure 21. Interfacing a PSD4235G2 with a H83/2350 29 30 31 32 CS7/IRQ3 CS6/IRQ2 IRQ1 IRQ0 11 12 13 14 16 17 18 19 20 21 22 23 25 26 27 28 85 83 55 53 57 56 54 58 90 89 91 RXD0 TXD0 SCK0 PXD1 TXD1 SCK1 RXD2 TXD2 SCK2 PF0/BREQ PF1/BACK PF2/LCAS/WAIT/B NMI PO0/TIOCA3 PO1/TIOCB3 PO2/TIOC3/TMRI PO3/TIOCD3/TMCI PO4/TIOCA4/TMRI PO5/TIOB4/TMRC PO6/TI0C5/TMRO PO7/TIOCB5/TMRO DREQ/CS4 TEND0/CS5 DREQ1 TEND1 MOD0 MOD1 MOD2 PF0/PHI0 RESET PO8/TIOCA0/DACK PO9/TIOCB0/DACK PO10/TIOCC0/TCL PO11/TIOCD0/TCL PO12/TIOCA1 PO13/TIOCB1/TCL PO14/TIOCA2 PO15/TIOCB2/TCL 88 87 86 74 71 70 69 68 67 66 65 64 60 61 62 63 113 114 115 80 RESET PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 A16 A17 A18 A19 RESET PSD4000 Series 49 GVDD0 GGND0 GVDD1 GGND1 HVDD HGND 99 98 110 111 122 123 Beta Information RESET RESET 127 133 134 137 138 QVCCH QVCC QGND JVDD JGND 50 D[15:0] D[15:0] A[21:0] A[21:0] VCC PSD4000 Series UI 9 VCC VCC VCC ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 21 22 23 24 25 26 27 28 D8 D9 D10 D11 D12 D13 D14 D15 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 31 32 33 34 35 36 37 38 D0 D1 D2 D3 D4 D5 D6 D7 29 69 U3 CRYATAL EXOSC XSOC DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 A8 A9 A10 A11 A12 A13 A14 A15 13 14 15 16 17 18 19 20 A16 A17 A18 A19 A20 A21 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 15 D0 D1 D2 D3 D4 D5 D6 D7 22 23 24 25 28 29 30 31 42 43 44 45 50 51 52 53 A0 A1 A2 A3 A4 A5 A6 A7 3 4 5 6 7 10 11 12 14 U2 D8 D9 D10 D11 D12 D13 D14 D15 32 33 34 35 38 39 40 41 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 135 136 TXD1/SIZ0 RXD1/SIZ1 UDS 40 CNTL2 (UDS) PD0 (AS) PD1 (CLKIN) PD2 (CSI) PD3 R/W LDS CSO* RESET 39 RESET 79 80 1 2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 GND GND GND GND GND 8 30 49 50 70 41 42 43 44 45 46 47 48 61 62 63 64 65 66 67 68 A16* A17 A18 A19 TXD0/PSTAT0 RXD0/PSTAT1 RTS0/PSTAT2 CTS0/PSTAT3 R/W OE EB1 EB0 CS0 CS1 CS2 CS3 75 76 79 80 SPI_MISO SPI_MISI SPI_EN SPI_CLK SPI_GP PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 COL7 COL6 COL5 COL4 COL3 COL2 COL1 COL0 QVCC QVCCH QGND CVDD CGND AVDD2 AGND2 AVDD1 AGND1 DVDD1 DGMD1 DVDD0 DGND0 QVCC QVCCH QVCCH QGND NOT USED AGND0 QGND QVCC 26 27 19 20 55 21 12 46 47 48 36 37 58 59 68 67 92 91 90 78 77 DE TDO TMS TD1 TCK TRST TEST IF GPS_OUT FVDD FGND CLKOUT CLKIN RSTOUT RSTIN LVRSTIN VBATT VSTBY 103 104 105 106 107 108 109 112 ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0 73 74 82 81 129 130 131 132 121 124 125 126 128 139 140 141 142 143 144 93 94 95 96 97 100 101 102 84 83 85 86 87 88 89 1 2 3 6 4 5 7 8 9 10 11 113 114 115 116 117 118 119 120 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 54 56 57 60 61 62 63 64 65 66 69 70 71 72 PSD4235G2 59 60 CRTL0 (R/W) CNTL1 (LDS) PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 51 52 53 54 55 56 57 58 Figure 22. Interfacing a PSD4235G2 with a MMC2001 MMC2001 71 72 73 74 75 76 77 78 PE0 (TMS) PE1 (TCK/ST) PE2 (TDI) PE3 (TDO) PE4 (TSTAT/RDY) PE5 (TERR) PE6 (VSTBY) PE7 (VBATON) 17 18 13 16 MOD XVDD XGND XGND A[19:16] A[19:16] AD[15:0] VCC VCC AD[15:0] Beta Information 144 136 129 109 93 9 VCC VCC VCC 29 69 138 XTAL1 U3 CRYATAL 137 XTAL2 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 ADIO8 ADI09 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 108 111 112 113 114 115 116 117 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 13 14 15 16 17 18 19 20 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 21 22 23 24 25 26 27 28 ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 VCC VCC VCC VCC VCC 100 101 102 103 104 105 106 107 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 3 4 5 6 7 10 11 12 31 32 33 34 35 36 37 38 VCC VCC VCC VCC VCC 82 72 56 46 17 65 66 67 68 69 70 73 74 75 76 77 78 P3.0/T0IN P3.1/T6OUT P3.2/CAPIN P3.4/T3TOUT P3.4/T3EUD P3.5/T4IN P3.6/T3IN P3.7/T2IN P3.8/MRST P3.10/TXD0 P3.10/TXD0 P3.11/RXD0 80 81 P3.13/SCLK P3.15/CLKOUT 59 60 CRTL0 (WR) CNTL1 (RD) CNTL2 (BHE) BHE 40 ALE WR RD 79 80 1 2 PDO (ALE) PD1 (CLKIN) PD2 (CSI) PD3 (WRH) C167CR P4.0/A16 A17 A18 A19 A20 A21 A22 P4.7/A23 WR/WRL RD P312/BHE/WRH ALE EA RESET 99 39 RESET PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 GND GND GND GND GND 8 30 49 50 70 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 85 86 87 88 89 90 91 92 96 95 79 98 A16 A17 A18 A19 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 51 52 53 54 55 56 57 58 PSD4235G2 Figure 23. Interfacing a PSD4235G2 with a C167CR 27 28 29 30 31 32 33 34 35 36 39 40 41 43 44 P5.0/AN0 P5.1/AN1 P5.2/AN2 P5.3/AN3 P5.4/AN4 P5.5/AN5 P5.6/AN6 P5.7/AN7 P5.9/AN8 P5.9/AN9 P5.10/AN10/T6UED P5.11/AN11/T5UED P5.12/AN12/T6IN P5.14/AN14/T4UED P5.15/AN15/T2UED P6.0/!CSO P6.1/!CS1 P6.2/!CS2 P6.3/!CS3 P6.4/!CS4 P6.5/!HOLD P6.6/!HLDA P6.7/!BREQ P7.0/POUT0 P7.1/POUT1 P7.2/POUT2 P7.3POUT/3 P7.4/CC28IO P7.5/CC29IO P7.6/CC30IO P7.7/CC31IO P8.0/CC16IO P8.1/CC17IO P8.2/CC18IO P8.3/CC19IO P8.4/CC20IO P8.5/CC21IO P8.6/CC22IO P8.7/CC23IO Vref READY P2.0/CC0IO P2.1/CC1IO P2.2/CC2IO P2.3/CC3IO P2.4/CC4IO P2.5/CC5IO P2.6/CC6IO P2.7/CC7IO P2.8/CC8IO/EX0IN P2.9/CC9IO/EX1IN P2.10CC10IO/EX2IN P2.11/CC11IO/EX3IN P2.12/CC12IO/EX4IN P2.13/CC13IO/EX5IN P2.14/CC14IO/EX6IN P2.15/CC15IO/EX7IN 140 141 142 RSTIN RSTOUT NMI VSS VSS VSS VSS VSS 143 139 127 110 94 83 VSS VSS VSS VSS VSS 71 55 45 18 AGND 38 47 48 49 50 51 52 53 54 57 58 59 60 61 62 63 64 P1H7 P1H6 P1H5 P1H4 P1H3 P1H2 P1H1 P1H0 P1L7 P1L6 P1L5 P1L4 P1L3 P1L2 P1L1 P1L0 71 72 73 74 75 76 77 78 135 134 133 132 131 130 129 128 125 124 123 122 121 120 119 118 PEO (TMS) PE1 (TCK/ST) PE2 (TDI) PD2 (TDO) PE4 (TSTAT/RDY) PE5 (TERR) PE6 (VSTBY) PE7 (VBATON) 1 2 3 4 5 6 7 8 19 20 21 22 23 24 25 26 9 10 11 12 13 14 15 16 A16 A17 A18 A19 37 97 RESET RESET PSD4000 Series 51 PSD4000 Series Beta Information The PSD4000 Functional Blocks (cont.) 9.4 I/O Ports There are seven programmable I/O ports: Ports A, B, C, D, E, F and G. Each of the ports is eight bits except Port D, which is 4 bits. Each port pin is individually user configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft or by the microcontroller writing to on-chip registers in the CSIOP address space. The topics discussed in this section are: * General Port Architecture * Port Operating Modes * Port Configuration Registers * Port Data Registers * Individual Port Functionality. 9.4.1 General Port Architecture The general architecture of the I/O Port is shown in Figure 24. Individual Port architectures are shown in Figures 26 through 28. In general, once the purpose for a port pin has been defined, that pin will no longer be available for other purposes. Exceptions will be noted. As shown in Figure 24, the ports contain an output multiplexer whose selects are driven by the configuration bits in the Control Registers (Ports E, F and G only) and PSDsoft Configuration. Inputs to the multiplexer include the following: Output data from the Data Out Register Latched address outputs CPLD MicroCell output External Chip Select from CPLD. The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be read. The PDB is connected to the Internal Data Bus for feedback and can be read by the microcontroller. The Data Out and MicroCell outputs, Direction and Control Registers, and port pin input are all connected to the PDB. The Port pin's tri-state output driver enable is controlled by a two input OR gate whose inputs come from the CPLD AND array enable product term and the Direction Register. If the enable product term of any of the array outputs are not defined and that port pin is not defined as a CPLD output in the PSDabel file, then the Direction Register has sole control of the buffer that drives the port pin. The contents of these registers can be altered by the microcontroller. The PDB feedback path allows the microcontroller to check the contents of the registers. Ports A, B, and C have embedded Input MicroCells (IMCs). The IMCs can be configured as latches, registers, or direct inputs to the PLDs. The latches and registers are clocked by the address strobe (AS/ALE) or a product term from the PLD AND array. The outputs from the IMCs drive the PLD input bus and can be read by the microcontroller. Refer to the IMC subsection of the PLD section. 52 Beta Information (cont.) The PSD4000 Functional Blocks DATA OUT REG. DATA OUT D WR ADDRESS D G OUTPUT MUX Q ADDRESS ALE MICRO CELL OUTPUTS EXT CS READ MUX P D DATA IN B OUTPUT SELECT Q Figure 24. General I/O Port Architecture PORT PIN INTERNAL DATA BUS CONTROL REG. D WR DIR REG. D WR ENABLE PRODUCT TERM (.OE) INPUT MICRO CELL CPLD-INPUT Q Q ENABLE OUT PSD4000 Series 53 PSD4000 Series Beta Information 9.4.2 Port Operating Modes The I/O Ports have several modes of operation. Some modes can be defined using PSDsoft, some by the microcontroller writing to the Registers in CSIOP space, and some by both. The modes that can only be defined using PSDsoft must be programmed into the device and cannot be changed unless the device is reprogrammed. The modes that can be changed by the microcontroller can be done so dynamically at run-time. The PLD I/O, Data Port, Address Input, Peripheral I/O and MCU Reset modes are the only modes that must be defined before programming the device. All other modes can be changed by the microcontroller at run-time. Table 19 summarizes which modes are available on each port. Table 22 shows how and where the different modes are configured. Each of the port operating modes are described in the following subsections. The PSD4000 Functional Blocks (cont.) Table 19. Port Operating Modes Port Mode MCU I/O PLD I/O McellA Outputs McellB Outputs Additional Ext. CS Outputs PLD Inputs Address Out Yes No No Yes No No Yes No Yes No No No Yes Yes No No No No Yes No No No No No Yes (A7-0) No No Yes Yes Yes (A7-0) No No No No Yes (A7-0) or (A15-8) No Yes No No Yes Port A Yes Port B Yes Port C Yes Port D Yes Port E Yes Port F Yes Port G Yes Address In Data Port Peripheral I/O JTAG ISP MCU Reset Mode** Yes No No No No Yes No No No No Yes No No No No Yes No No No No No No No Yes* No Yes Yes Yes No Yes **Can be multiplexed with other I/O functions. **Available to Motorola 16-bit 683XX and HC16 family of MCUs. 54 Beta Information PSD4000 Series The PSD4000 Functional Blocks (cont.) Table 20. Port Operating Mode Settings Defined In PSDsoft Declare pins only Declare pins and logic equations Selected for MCU with non-mux bus Declare pins only Mode MCU I/O Control Register Setting 0 (Note 3) Direction Register Setting 1 = output, 0 = input (Note 1) (Note 1) VM Register Setting NA JTAG Enable NA PLD I/O NA NA NA Data Port (Port F, G) Address Out (Port E, F, G) NA NA NA NA 1 1 (Note 1) NA NA Declare pins or Address In logic equation (Port A,B,C,D,F) for input MicroCells Peripheral I/O (Port F) JTAG ISP (Note 2) MCU Reset Mode Logic equations (PSEL0 & 1) Declare pins only Specify pin logic level NA NA NA NA NA NA PIO bit = 1 NA NA NA NA NA NA NA JTAG_Enable NA *NA = Not Applicable NOTE: 1. The direction of the Port A,B,C, and F pins are controlled by the Direction Register ORed with the individual output enable product term (.oe) from the CPLD AND array. 2. Any of these three methods will enable JTAG pins on Port E. 3. Control Register setting is not applicable to Ports A, B and C. 9.4.2.1 MCU I/O Mode In the MCU I/O Mode, the microcontroller uses the PSD4000 ports to expand its own I/O ports. By setting up the CSIOP space, the ports on the PSD4000 are mapped into the microcontroller address space. The addresses of the ports are listed in Table 6. A port pin can be put into MCU I/O mode by writing a `0' to the corresponding bit in the Control Register (Port E, F and G). The MCU I/O direction may be changed by writing to the corresponding bit in the Direction Register, or by the output enable product term. See the subsection on the Direction Register in the "Port Registers" section. When the pin is configured as an output, the content of the Data Out Register drives the pin. When configured as an input, the microcontroller can read the port input through the Data In buffer. See Figure 24. Ports A, B and C do not have Control Registers, and are in MCU I/O mode by default. They can be used for PLD I/O if they are specified in PSDsoft. 9.4.2.2 PLD I/O Mode The PLD I/O Mode uses a port as an input to the CPLD's Input MicroCells, and/or as an output from the CPLD's Output MicroCells. The output can be tri-stated with a control signal. This output enable control signal can be defined by a product term from the PLD, or by setting the corresponding bit in the Direction Register to `0'. The corresponding bit in the Direction Register must not be set to `1' if the pin is defined as a PLD input pin in PSDsoft. The PLD I/O Mode is specified in PSDsoft by declaring the port pins, and then specifying an equation in PSDsoft. 55 PSD4000 Series Beta Information 9.4.2.3 Address Out Mode For microcontrollers with a multiplexed address/data bus, Address Out Mode can be used to drive latched addresses onto the port pins. These port pins can, in turn, drive external devices. Either the output enable or the corresponding bits of both the Direction Register and Control Register must be set to a `1' for pins to use Address Out Mode. This must be done by the MCU at run-time. See Table 21 for the address output pin assignments on Ports E, F and F for various MCUs. Note: Do not drive address lines with Address Out Mode to an external memory device if it is intended for the MCU to boot from the external device. The MCU must first boot from PSD memory so the Direction and Control register bits can be set. The PSD4000 Functional Blocks (cont.) Table 21. I/O Port Latched Address Output Assignments MCU 80C51XA All Other MCU with Multiplexed Bus Port E (3:0) N/A Port E (7:4) Addr (7:4) Port F (3:0) N/A Port F (7:4) Addr (7:4) Port G (3:0) Addr (11:8) Port G (7:4) Addr (15:12) Addr (3:0) Addr (7:4) Addr (3:0) Addr (7:4) Addr (11:8) Addr (15:12) 9.4.2.4 Address In Mode For microcontrollers that have more than 16 address lines, the higher addresses can be connected to Ports A, B, C, D or F and are routed as inputs to the PLDs. The address input can be latched in the Input MicroCell by the address strobe (ALE/AS). Any input that is included in the DPLD equations for the Main Flash, Boot Flash, or SRAM is considered to be an address input. 9.4.2.5 Data Port Mode Port F and G can be used as a data bus port for a microcontroller with a non-multiplexed address/data bus. The Data Port is connected to the data bus of the microcontroller. The general I/O functions are disabled in Port F and G if the ports are configured as Data Port. Data Port Mode is automatically configured in PSDsoft when a non-multiplexed bus MCU is selected. 9.4.2.6 Peripheral I/O Mode Peripheral I/O Mode can be used to interface with external 8-bit peripherals. In this mode, all of Port F serves as a tri-stateable, bi-directional data buffer for the microcontroller. Peripheral I/O Mode is enabled by setting Bit 7 of the VM Register to a `1'. Figure 25 shows how Port A acts as a bi-directional buffer for the microcontroller data bus if Peripheral I/O Mode is enabled. An equation for PSEL0 and/or PSEL1 must be specified in PSDsoft. The buffer is tri-stated when PSEL 0 or 1 is not active. 9.4.2.7 JTAG ISP Port E is JTAG compliant, and can be used for In-System Programming (ISP). You can multiplex JTAG operations with other functions on Port E because ISP is not performed during normal system operation. For more information on the JTAG Port, refer to section 9.6. 56 Beta Information PSD4000 Series 9.4.2.8 MCU Reset Mode Port F and G can be configured to operate in "MCU Reset" mode. This mode is available when PSD is configured for the Motorola 16-bit 683XX and HC16 family and is active only during reset. At the rising edge of the Reset input, the MCU reads the logic level on the Data Bus D15-0 pins. The MCU then configures some of its I/O pin functions according to the logic level input on the data bus lines. Two dedicated buffers are usually enabled during reset to drive the data bus lines to the desired logic level. The PSD4235G2 can replace the two buffers by configuring Port F and G to operate in MCU Reset Mode. In this mode, the PSD will drive the pre-defined logic level or data pattern onto the MCU Data Bus when reset is active and there is no ongoing bus cycle. After reset, Port F and G return to the normal Data Port Mode. The MCU Reset Mode is enabled and configured in PSDsoft. The user defines the logic level (data pattern) that will be driven out from Port F and G during reset. The PSD4000 Functional Blocks (cont.) Figure 25. Peripheral I/O Mode RD PSEL0 PSEL PSEL1 D0 - D7* DATA BUS VM REGISTER BIT 7 PF0 - PF7 WR *NOTE D8-D15 for 16-bit Motorola MCU. 9.4.3 Port Configuration Registers (PCRs) Each port has a set of PCRs used for configuration. The contents of the registers can be accessed by the microcontroller through normal read/write bus cycles at the addresses given in Table 6. The addresses in Table 6 are the offsets in hex from the base of the CSIOP register. The pins of a port are individually configurable and each bit in the register controls its respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three PCRs, shown in Table 22, are used for setting the port configurations. The default power-up state for each register in Table 22 is 00h. Table 22. Port Configuration Registers Register Name Control Direction Drive Select* *NOTE: Port E,F,G A,B,C,D,E,F,G A,B,C,D,E,F,G MCU Access Write/Read Write/Read Write/Read See Table 26 for Drive Register bit definition. 57 PSD4000 Series Beta Information 9.4.3.1 Control Register Any bit set to `0' in the Control Register sets the corresponding Port pin to MCU I/O Mode, and a `1' sets it to Address Out Mode. The default mode is MCU I/O. Only Ports E, F and G have an associated Control Register. 9.4.3.2 Direction Register The Direction Register controls the direction of data flow in the I/O Ports. Any bit set to `1' in the Direction Register will cause the corresponding pin to be an output, and any bit set to `0' will cause it to be an input. The default mode for all port pins is input. Figures 26 and 28 show the Port Architecture diagrams for Ports A/B/C and E/F/G respectively. The direction of data flow for Ports A, B, C and F are controlled not only by the direction register, but also by the output enable product term from the PLD AND array. If the output enable product term is not active, the Direction Register has sole control of a given pin's direction. An example of a configuration for a port with the three least significant bits set to output and the remainder set to input is shown in Table 25. Since Port D only contains four pins, the Direction Register for Port D has only the four least significant bits active. The PSD4000 Functional Blocks (cont.) Table 23. Port Pin Direction Control, Output Enable P.T. Not Defined Direction Register Bit Port Pin Mode 0 1 Input Output Table 24. Port Pin Direction Control, Output Enable P.T. Defined Direction Register Bit Output Enable P.T. Port Pin Mode 0 0 1 1 0 1 0 1 Input Output Output Output Table 25. Port Direction Assignment Example Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 1 Bit 1 1 Bit 0 1 58 Beta Information PSD4000 Series 9.4.3.3 Drive Select Register The Drive Select Register configures the pin driver as Open Drain or CMOS for some port pins, and controls the slew rate for the other port pins. An external pull-up resistor should be used for pins configured as Open Drain. A pin can be configured as Open Drain if its corresponding bit in the Drive Select Register is set to a `1'. The default pin drive is CMOS. Aside: the slew rate is a measurement of the rise and fall times of an output. A higher slew rate means a faster output response and may create more electrical noise. A pin operates in a high slew rate when the corresponding bit in the Drive Register is set to `1'. The default rate is slow slew. Table 26 shows the Drive Register for Ports A, B, C, D, E, F and G. It summarizes which pins can be configured as Open Drain outputs and which pins the slew rate can be set for. The PSD4000 Functional Blocks (cont.) Table 26. Drive Register Pin Assignment Drive Register Port A Port B Port C Port D Port E Port F Port G Open Drain Slew Rate Open Drain Open Drain Slew Rate Open Drain Open Drain Slew Rate Open Drain Open Drain Slew Rate Open Drain Bit 7 Open Drain Open Drain Slew Rate Bit 6 Open Drain Open Drain Slew Rate Bit 5 Open Drain Open Drain Slew Rate Bit 4 Open Drain Open Drain Slew Rate Bit 3 Open Drain Open Drain Slew Rate Open Drain Open Drain Slew Rate Open Drain Bit 2 Open Drain Open Drain Slew Rate Open Drain Open Drain Slew Rate Open Drain Bit 1 Open Drain Open Drain Slew Rate Open Drain Open Drain Slew Rate Open Drain Bit 0 Open Drain Open Drain Slew Rate Open Drain Open Drain Slew Rate Open Drain 59 PSD4000 Series Beta Information The PSD4000 Functional Blocks (cont.) 9.4.4 Port Data Registers The Port Data Registers, shown in Table 27, are used by the microcontroller to write data to or read data from the ports. Table 27 shows the register name, the ports having each register type, and microcontroller access for each register type. The registers are described below. 9.4.4.1 Data In Port pins are connected directly to the Data In buffer. In MCU I/O input mode, the pin input is read through the Data In buffer. 9.4.4.2 Data Out Register Stores output data written by the MCU in the MCU I/O output mode. The contents of the Register are driven out to the pins if the Direction Register or the output enable product term is set to "1". The contents of the register can also be read back by the microcontroller. 9.4.4.3 Output MicroCells (OMCs) The CPLD OMCs occupy a location in the microcontroller's address space. The microcontroller can read the output of the OMCs. If the Mask MicroCell Register bits are not set, writing to the MicroCell loads data to the MicroCell flip flops. Refer to the PLD section for more details. 9.4.4.4 Mask MicroCell Register Each Mask Register bit corresponds to an OMC flip flop. When the Mask Register bit is set to a "1", loading data into the OMC flip flop is blocked. The default value is "0" or unblocked. 9.4.4.5 Input MicroCells (IMCs) The IMCs can be used to latch or store external inputs. The outputs of the IMCs are routed to the PLD input bus, and can be read by the microcontroller. Refer to the PLD section for a detailed description. 9.4.4.6 Enable Out The Enable Out register can be read by the microcontroller. It contains the output enable values for a given port. A "1" indicates the driver is in output mode. A "0" indicates the driver is in tri-state and the pin is in input mode. Table 27. Port Data Registers Register Name Data In Data Out Output MicroCell Mask MicroCell Input MicroCell Enable Out Port A,B,C,D,E,F,G A,B,C,D,E,F,G A,B A,B A,B,C A,B,C,F Write/Read MCU Access Read - input on pin Read - outputs of MicroCells Write - loading MicroCells Flip-Flop Write/Read - prevents loading into a given MicroCell Read - outputs of the Input MicroCells Read - the output enable control of the port driver 60 Beta Information PSD4000 Series The PSD4000 Functional Blocks (cont.) 9.4.5 Ports A, B and C - Functionality and Structure Ports A and B have similar functionality and structure, as shown in Figure 26. The two ports can be configured to perform one or more of the following functions: MCU I/O Mode CPLD Output - MicroCells McellA[7:0] can be connected to Port A. McellB[7:0] can be connected to Port B. External chip select ECS [7:0] can be connected to Port C. CPLD Input - Via the input MicroCells. Address In - Additional high address inputs using the Input MicroCells. Open Drain/Slew Rate - pins PC[7:0]can be configured to fast slew rate, pins PA[7:0] and PB[7:0] can be configured to Open Drain Mode. Figure 26. Port A, B and C PORT PIN OUTPUT MUX DATA OUT OUTPUT SELECT DATA IN ENABLE OUT ENABLE PRODUCT TERM (.OE) INPUT MICRO CELL MCELLA [ 7:0 ] (PORT A) MCELLB [ 7:0 ] (PORT B) WR EXT.CS (PORT C) WR CPLD-INPUT READ MUX DATA OUT REG. DIR REG. Q D D B P D Q INTERNAL DATA BUS 61 PSD4000 Series Beta Information The PSD4000 Functional Blocks (cont.) 9.4.6 Port D - Functionality and Structure Port D has four I/O pins. See Figure 27. Port D can be configured to program one more of the following functions: MCU I/O Mode CPLD Input - direct input to CPLD, no Input MicroCells Port D pins can be configured in PSDsoft as input pins for other dedicated functions: PD0 - ALE, as address strobe input PD1 - CLKIN, as clock input to the MicroCells Flip Flops and APD counter PD2 - CSI, as active low chip select input. A high input will disable the Flash/SRAM and CSIOP. PD3 - WRH, as active low Write Enable (high byte) input or as DBE input from 68HC912 9.4.7 Port E - Functionality and Structure Port E can be configured to perform one or more of the following functions (see Figure 28): MCU I/O Mode In-System Programming - JTAG port can be enabled for programming/erase of the PSD4000 device. (See Section 9.6 for more information on JTAG programming.) Open Drain - Port E pins can be configured in Open Drain Mode Battery Backup features - PE6 can be configured as a Battery Input (Vstby) pin. PE7 can be configured as a Battery On Indicator output pin, indicating when Vcc is less than Vbat. Latched Address Output - Provided latched address (A7-0) output Figure 27. Port D Structure DATA OUT REG. DATA OUT D WR OUTPUT MUX Q PORT D PIN INTERNAL DATA BUS READ MUX P D B DATA IN OUTPUT SELECT DIR REG. D WR Q CPLD-INPUT 62 Beta Information PSD4000 Series The PSD4000 Functional Blocks (cont.) 9.4.8 Port F - Functionality and Structure Port F can be configured to perform one or more of the following functions: MCU I/O Mode CPLD Output - external chip select ECS[7:0] can be connected to Port F (or Port C). CPLD Input - as direct input ot the CPLD array. Address In - additional high address inputs. Direct input to the CPLD array, no Input MicroCells latching is available. Latched Address Out - Provide latched address out per Table 29. Slew Rate - pins can be set up for fast slew rate. Data Port - connected to D[7:0] when Port F is configured as Data Port for a non-multiplexed bus. Peripheral I/O Mode MCU Reset Mode - for 16-bit Motorola 683XX and HC16 microcontrollers. 9.4.9 Port G - Functionality and Structure Port G can be configured to perform one or more of the following functions: MCU I/O Mode Latched Address Out - provide latched address out per Table 29. Open Drain - pins can be configured in Open Drain Mode Data Port - connected to D[15:8] when Port G is configured as Data Port for a non-multiplexed bus. MCU Reset Mode - for 16-bit Motorola 683XX and HC16 microcontrollers Figure 28. Ports E, F and G Structure DATA OUT REG. D WR ADDRESS ALE D G Q ADDRESS A[ 7:0] OR A[15:8] PORT PIN OUTPUT MUX Q DATA OUT EXT. CS (PORT F) READ MUX P D B CONTROL REG. D WR DIR REG. D WR ENABLE PRODUCT TERM (.OE) CPLD INPUT (PORT F) ISP OR BATTERY BACK-UP (PORT E) CONFIGURATION BIT Q Q ENABLE OUT DATA IN OUTPUT SELECT INTERNAL DATA BUS 63 PSD4000 Series Beta Information The PSD4000 Functional Blocks (cont.) 9.5 Power Management The PSD4000 offers configurable power saving options. These options may be used individually or in combinations, as follows: All memory types in a PSD (Flash, Secondary Flash, and SRAM) are built with Zero-Power technology. In addition to using special silicon design methodology, Zero-Power technology puts the memories into standby mode when address/data inputs are not changing (zero DC current). As soon as a transition occurs on an input, the affected memory "wakes up", changes and latches its outputs, then goes back to standby. The designer does not have to do anything special to achieve memory standby mode when no inputs are changing--it happens automatically. The PLD sections can also achieve standby mode when its inputs are not changing, see PMMR registers below. Like the Zero-Power feature, the Automatic Power Down (APD) logic allows the PSD to reduce to standby current automatically. The APD will block MCU address/data signals from reaching the memories and PLDs. This feature is available on all PSD4000 devices. The APD unit is described in more detail in section 9.5.1. Built in logic will monitor the address strobe of the MCU for activity. If there is no activity for a certain time period (MCU is asleep), the APD logic initiates Power Down Mode (if enabled). Once in Power Down Mode, all address/data signals are blocked from reaching PSD memories and PLDs, and the memories are deselected internally. This allows the memories and PLDs to remain in standby mode even if the address/data lines are changing state externally (noise, other devices on the MCU bus, etc.). Keep in mind that any unblocked PLD input signals that are changing states keeps the PLD out of standby mode, but not the memories. The PSD Chip Select Input (CSI) can be used to disable the internal memories, placing them in standby mode even if inputs are changing. This feature does not block any internal signals or disable the PLDs. This is a good alternative to using the APD logic, especially if your MCU has a chip select output. There is a slight penalty in memory access time when the CSI signal makes its initial transition from deselected to selected. The PMMR registers can be written by the MCU at run-time to manage power. All PSD devices support "blocking bits" in these registers that are set to block designated signals from reaching both PLDs. Current consumption of the PLDs is directly related to the composite frequency of the changes on their inputs (see Figures 32 and 32a). Significant power savings can be achieved by blocking signals that are not used in PLD logic equations at run time. PSDsoft creates a fuse map that automatically blocks the low address byte (A7-A0) or the control signals (CNTL0-2, ALE and WRH/DBE) if none of these signals are used in PLD logic equations. The PSD4000 devices have a Turbo Bit in the PMMR0 register. This bit can be set to disable the Turbo Mode feature (default is Turbo Mode on). While Turbo Mode is disabled, the PLDs can achieve standby current when no PLD inputs are changing (zero DC current). Even when inputs do change, significant power can be saved at lower frequencies (AC current), compared to when Turbo Mode is enabled. Conversely, when the Turbo Mode is enabled, there is a significant DC current component and the AC component is higher. 9.5.1 Automatic Power Down (APD) Unit and Power Down Mode The APD Unit, shown in Figure 29, puts the PSD into Power Down Mode by monitoring the activity of the address strobe (ALE/AS). If the APD unit is enabled, as soon as activity on the address strobe stops, a four bit counter starts counting. If the address strobe remains inactive for fifteen clock periods of the CLKIN signal, the Power Down (PDN) signal becomes active, and the PSD will enter into Power Down Mode, discussed next. 64 Beta Information PSD4000 Series 9.5.1 Automatic Power Down (APD) Unit and Power Down Mode (cont.) Power Down Mode By default, if you enable the PSD APD unit, Power Down Mode is automatically enabled. The device will enter Power Down Mode if the address strobe (ALE/AS) remains inactive for fifteen CLKIN (pin PD1) clock periods. The following should be kept in mind when the PSD is in Power Down Mode: The PSD4000 Functional Blocks (cont.) * If the address strobe starts pulsing again, the PSD will return to normal operation. * * The PSD will also return to normal operation if either the CSI input returns low or the Reset input returns high. The MCU address/data bus is blocked from all memories and PLDs. Various signals can be blocked (prior to Power Down Mode) from entering the PLDs by setting the appropriate bits in the PMMR registers. The blocked signals include MCU control signals and the common clock (CLKIN). Note that blocking CLKIN from the PLDs will not block CLKIN from the APD unit. All PSD memories enter Standby Mode and are drawing standby current. However, the PLDs and I/O ports do not go into Standby Mode because you don't want to have to wait for the logic and I/O to "wake-up" before their outputs can change. See Table 28 for Power Down Mode effects on PSD ports. Typical standby current is 50 A for 5 V parts. This standby current value assumes that there are no transitions on any PLD input. * * Table 28. Power Down Mode's Effect on Ports Port Function MCU I/O PLD Out Address Out Data Port Peripheral I/O Pin Level No Change No Change Undefined Three-State Three-State Table 29. PSD4000 Timing and Standby Current During Power Down Mode PLD Propagation Delay Normal tpd (Note 1) Mode Power Down Memory Access Time No Access Access Recovery Time to Normal Access tLVDV 5V VCC, Typical Standby Current 50 A (Note 2) NOTES: 1. Power Down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo Bit. 2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo bit is off. 65 PSD4000 Series Beta Information The PSD4000 Functional Blocks (cont.) Figure 29. APD Logic Block APD EN PMMR0 BIT 1=1 TRANSITION DETECTION ALE CLR PD SECONDARY FLASH SELECT MAIN FLASH SELECT PLD SRAM SELECT POWER DOWN (PDN) SELECT DISABLE BUS INTERFACE RESET CSI CLKIN DISABLE MAIN AND SECONDARY FLASH/SRAM EDGE DETECT APD COUNTER PD Figure 30. Enable Power Down Flow Chart RESET Enable APD Set PMMR0 Bit 1 = 1 OPTIONAL Disable desired inputs to PLD by setting PMMR0 bits 4 and 5 and PMMR2 bits 0. No ALE/AS idle for 15 CLKIN clocks? Yes PSD in Power Down Mode 66 Beta Information PSD4000 Series The PSD4000 Functional Blocks (cont.) Table 30. Power Management Mode Registers (PMMR0, PMMR2)** PMMR0 Bit 7 Bit 6 Bit 5 PLD Mcell clk 1 = off Bit 4 PLD Array clk 1 = off Bit 3 PLD Turbo 1 = off Bit 2 Bit 1 APD Enable 1 = on Bit 0 * * * * ***Bits 0, 2, 6, and 7 are not used, and should be set to 0. ***The PMMR0, and PMMR2 register bits are cleared to zero following power up. ***Subsequent reset pulses will not clear the registers. Bit 1 0 1 Bit 3 0 1 Bit 4 0 Automatic Power Down (APD) is disabled. Automatic Power Down (APD) is enabled. PLD Turbo is on. PLD Turbo is off, saving power. CLKIN input to the PLD AND array is connected. Every CLKIN change will power up the PLD when Turbo bit is off. 1 = CLKIN input to PLD AND array is disconnected, saving power. Bit 5 0 = CLKIN input to the PLD MicroCells is connected. 1 = CLKIN input to PLD MicroCells is disconnected, saving power. PMMR2 Bit 7 * Bit 6 PLD array WRH/DBE 1 = off = = = = = Bit 5 PLD array ALE 1 = off Bit 4 PLD** array CNTL2 1 = off Bit 3 PLD** array CNTL1 1 = off Bit 2 PLD** array CNTL0 1 = off Bit 1 * Bit 0 PLD array Addr. 1 = off **Unused bits should be set to 0. **Refer to Table 14 the signals that are blocked on pins CNTL0-2. Bit 0 0 = Address A[7:0] inputs to the PLD AND array are connected. 1 = Address A[7:0] inputs to the PLD AND array are disconnected, saving power. Note: In 80C51XA mode, A[7:1] comes from Port F (PF1-PF3) and AD10 [3:0]. Bit 2 0 = Cntl0 input to the PLD AND array is connected. 1 = Cntl0 input to PLD AND array is disconnected, saving power. Bit 3 0 = Cntl1 input to the PLD AND array is connected. 1 = Cntl1 input to PLD AND array is disconnected, saving power. Bit 4 0 = Cntl2 input to the PLD AND array is connected. 1 = Cntl2 input to PLD AND array is disconnected, saving power. Bit 5 0 = ALE input to the PLD AND array is connected. 1 = ALE input to PLD AND array is disconnected, saving power. Bit 6 0 = WRH/DBE input to the PLD AND array is connected. 1 = WRH/DBE input to PLD AND array is disconnected, saving power. 67 PSD4000 Series Beta Information The PSD4000 Functional Blocks (cont.) Table 31. APD Counter Operation APD Enable Bit 0 1 1 1 ALE PD Polarity X X 1 0 ALE Level X Pulsing 1 0 APD Counter Not Counting Not Counting Counting (Generates PDN after 15 Clocks) Counting (Generates PDN after 15 Clocks) 9.5.2 Other Power Saving Options The PSD4000 offers other reduced power saving options that are independent of the Power Down Mode. Except for the SRAM Standby and CSI input features, they are enabled by setting bits in the PMMR0 and PMMR2 registers. 9.5.2.1 Zero Power PLD The power and speed of the PLDs are controlled by the Turbo bit (bit 3) in the PMMR0. By setting the bit to "1", the Turbo mode is disabled and the PLDs consume Zero Power current when the inputs are not switching for an extended time of 70 ns. The propagation delay time will be increased after the Turbo bit is set to "1" (turned off) when the inputs change at a composite frequency of less than 15 MHz. When the Turbo bit is set to a "0" (turned on), the PLDs run at full power and speed. The Turbo bit affects the PLD's D.C. power, AC power, and propagation delay. Refer to AC/DC spec for PLD timings. Note: Blocking MCU control signals with PMMR2 bits can further reduce PLD AC power consumption. 9.5.2.2 SRAM Standby Mode (Battery Backup) The PSD4000 supports a battery backup operation that retains the contents of the SRAM in the event of a power loss. The SRAM has a Vstby pin (PE6) that can be connected to an external battery. When VCC becomes lower than Vstby then the PSD will automatically connect to Vstby as a power source to the SRAM. The SRAM Standby Current (Istby) is typically 0.5 A. The SRAM data retention voltage is 2 V minimum. The battery-on indicator (Vbaton) can be routed to PE7. This signal indicates when the VCC has dropped below the Vstby voltage and that the SRAM is running on battery power. 9.5.2.3 The CSI Input Pin PD2 of Port D can be configured in PSDsoft as the CSI input. When low, the signal selects and enables the internal Flash, Boot Block, SRAM, and I/O for read or write operations involving the PSD4000. A high on the CSI pin will disable the Flash memory, Boot Block, and SRAM, and reduce the PSD power consumption. However, the PLD and I/O pins remain operational when CSI is high. Note: there may be a timing penalty when using the CSI pin depending on the speed grade of the PSD that you are using. See the timing parameter t SLQV in the AC/DC specs. 9.5.2.4 Input Clock The PSD4000 provides the option to turn off the CLKIN input to the PLD to save AC power consumption. The CLKIN is an input to the PLD AND array and the Output MicroCells. During Power Down Mode, or, if the CLKIN input is not being used as part of the PLD logic equation, the clock should be disabled to save AC power. The CLKIN will be disconnected from the PLD AND array or the MicroCells by setting bits 4 or 5 to a "1" in PMMR0. 9.5.2.5 MCU Control Signals The PSD4000 provides the option to turn off the address input (A7-0) and input control signals (CNTL0-2, ALE, and WRH/DBE) to the PLD to save AC power consumption. These signals are inputs to the PLD AND array. During Power Down Mode, or, if any of them are not being used as part of the PLD logic equation, these control signals should be disabled to save AC power. They will be disconnected from the PLD AND array by setting bits 0, 2, 3, 4, 5, and 6 to a "1" in the PMMR2. 68 Beta Information PSD4000 Series The PSD4000 Functional Blocks (cont.) 9.5.3 Reset and Power On Requirement 9.5.3.1 Power On Reset Upon power up the PSD4000 requires a reset pulse of tNLNH-PO (minimum 1 ms) after VCC is steady. During this time period the device loads internal configurations, clears some of the registers and sets the Flash into operating mode. After the rising edge of reset, the PSD4000 remains in the reset state for an additional tOPR (maximum 120 ns) nanoseconds before the first memory access is allowed. The PSD4000 Flash memory is reset to the read array mode upon power up. The FSi and CSBOOTi select signals along with the write strobe signal must be in the false state during power-up reset for maximum security of the data contents and to remove the possibility of data being written on the first edge of a write strobe signal. Any Flash memory write cycle initiation is prevented automatically when VCC is below VLKO. 9.5.3.2 Warm Reset Once the device is up and running, the device can be reset with a much shorter pulse of tNLNH (minimum 150 ns). The same tOPR time is needed before the device is operational after warm reset. Figure 31 shows the timing of the power on and warm reset. Figure 31. Power On and Warm Reset Timing OPERATING LEVEL t NLNH - PO VCC t NLNH t NLNH-A RESET t OPR POWER ON RESET WARM RESET t OPR 9.5.3.3 I/O Pin, Register and PLD Status at Reset Table 32 shows the I/O pin, register and PLD status during power on reset, warm reset and power down mode. PLD outputs are always valid during warm reset, and they are valid in power on reset once the internal PSD configuration bits are loaded. This loading of PSD is completed typically long before the VCC ramps up to operating level. Once the PLD is active, the state of the outputs are determined by the equations specified in PSDsoft. 69 PSD4000 Series Beta Information The PSD4000 Functional Blocks (cont.) Table 32. Status During Power On Reset, Warm Reset and Power Down Mode Port Configuration MCU I/O PLD Output Power On Reset Input Mode Valid after internal PSD configuration bits are loaded Tri-stated Tri-stated Tri-stated Warm Reset Input Mode Valid Power Down Mode Unchanged Depend on inputs to PLD (address are blocked in PD mode) Not defined Tri-stated Tri-stated Address Out Data Port Peripheral I/O Tri-stated Tri-stated Tri-stated Register PMMR0, 2 MicroCells Flip Flop status VM Register* Power On Reset Cleared to "0" Cleared to "0" by internal power on reset Initialized based on the selection in PSDsoft Configuration Menu. Cleared to "0" Warm Reset Unchanged Depend on .re and .pr equations Power Down Mode Unchanged Depend on .re and .pr equations Initialized based on Unchanged the selection in PSDsoft Configuration Menu. Cleared to "0" Unchanged All other registers *SR_cod and Periph Mode bits in the VM Register are always cleared to zero on power on or warm reset. ** 9.5.3.4 Reset of Flash Erase and Programming Cycles An external reset on the RESET pin will also reset the internal Flash memory state machine. When the Flash is in programming or erase mode, the RESET pin will terminate the programming or erase operation and return the Flash back to read mode in tNLNH-A (minimum 25 s) time. 9.6 Programming In-Circuit using the JTAG-ISP Interface The JTAG-ISP interface on the PSD4000 can be enabled on Port E (see Table 33). All memory (Flash and Flash Boot Block), PLD logic, and PSD configuration bits may be programmed through the JTAG-ISC interface. A blank part can be mounted on a printed circuit board and programmed using JTAG-ISP. The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional signals, TSTAT and TERR, are optional JTAG extensions used to speed up program and erase operations. By default, on a blank PSD (as shipped from factory or after erasure), four pins on Port E are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO. See Waferscale Application Note 54 for more details on JTAG In-System-Programming. Table 33. JTAG Port Signals Port E Pin PE0 PE1 PE2 PE3 PE4 PE5 70 JTAG Signals TMS TCK TDI TDO TSTAT TERR Description Mode Select Clock Serial Data In Serial Data Out Status Error Flag Beta Information PSD4000 Series 9.6.1 Standard JTAG Signals The standard JTAG signals (TMS, TCK, TDI, and TDO) can be enabled by any of three different conditions that are logically ORed. When enabled, TDI, TDO, TCK, and TMS are inputs, waiting for a serial command from an external JTAG controller device (such as FlashLink or Automated Test Equipment). When the enabling command is received from the external JTAG controller, TDO becomes an output and the JTAG channel is fully functional inside the PSD. The same command that enables the JTAG channel may optionally enable the two additional JTAG pins, TSTAT and TERR. The following symbolic logic equation specifies the conditions enabling the four basic JTAG pins (TMS, TCK, TDI, and TDO) on their respective Port E pins. For purposes of discussion, the logic label JTAG_ON will be used. When JTAG_ON is true, the four pins are enabled for JTAG. When JTAG_ON is false, the four pins can be used for general PSD I/O. JTAG_ON = PSDsoft_enabled + /* An NVM configuration bit inside the PSD is set by the designer in the PSDsoft Configuration utility. This dedicates the pins for JTAG at all times (compliant with IEEE 1149.1) */ Microcontroller_enabled + /* The microcontroller can set a bit at run-time by writing to the PSD register, JTAG Enable. This register is located at address CSIOP + offset C7h. Setting the JTAG_ENABLE bit in this register will enable the pins for JTAG use. This bit is cleared by a PSD reset or the microcontroller. See Table 35 for bit definition. */ PSD_product_term_enabled; /* A dedicated product term (PT) inside the PSD can be used to enable the JTAG pins. This PT has the reserved name JTAGSEL. Once defined as a node in PSDabel, the designer can write an equation for JTAGSEL. This method is used when the Port E JTAG pins are multiplexed with other I/O signals. It is recommended to logically tie the node JTAGSEL to the JEN\ signal on the Flashlink cable when multiplexing JTAG signals. See Application Note 54 for details. The PSD4000 Functional Blocks (cont.) Table 34. JTAG Enable Register JTAG Enable Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 JTAG_ENABLE * * * * * * * *Bits 1-7 are not used and should set to 0. Bit definitions: JTAG_ENABLE 1 = JTAG Port is Enabled. 0 = JTAG Port is Disabled. NOTE: The state of the PSD reset input signal will not interrupt (or prevent) JTAG operations if the JTAG pins are dedicated by an NVM configuration bit (via PSDsoft). However, the PSD reset input will prevent or interrupt JTAG operations if the JTAG enable register is used to enable the JTAG pins. 71 PSD4000 Series Beta Information The PSD4000 Functional Blocks (cont.) 9.6.1 Standard JTAG Signals (cont.) The PSD4000 supports JTAG-ISP commands, but not Boundary Scan. Waferscale's PSDsoft software tool and FlashLink JTAG programming cable implement these JTAG-ISP commands. 9.6.2 JTAG Extensions TSTAT and TERR are two JTAG extension signals enabled by a JTAG command received over the four standard JTAG pins (TMS, TCK, TDI, and TDO). They are used to speed programming and erase functions by indicating status on PSD pins instead of having to scan the status out serially using the standard JTAG channel. See Application Note 54. TERR will indicate if an error has occurred when erasing a sector or programming in Flash memory. This signal will go low (active) when an error condition occurs, and stay low until a special JTAG command is executed or a chip reset pulse is received after an "ISC-DISABLE" command. TSTAT behaves the same as the Rdy/Bsy signal described in section 9.1.1.2. TSTAT will be high when the PSD4000 device is in read array mode (Flash memory and Boot Block contents can be read). TSTAT will be low when Flash memory programming or erase cycles are in progress, and also when data is being written to the Flash Boot Block. TSTAT and TERR can be configured as open-drain type signals with a JTAG command. 9.6.3 Security and Flash Memories Protection When the security bit is set, the device cannot be read on a device programmer or through the JTAG Port. When using the JTAG Port, only a full chip erase command is allowed. All other program/erase/verify commands are blocked. Full chip erase returns the part to a non-secured blank state. The Security Bit can be set in PSDsoft. All Flash Memory and Boot sectors can individually be sector protected against erasures. The sector protect bits can be set in PSDsoft. 72 Beta Information PSD4000 Series 10.0 Absolute Maximum Ratings Symbol TSTG Parameter Storage Temperature Operating Temperature Voltage on any Pin Condition PLDCC Commercial Industrial With Respect to GND With Respect to GND With Respect to GND Min - 65 0 - 40 - 0.6 - 0.6 - 0.6 Max + 125 + 70 + 85 +7 + 14 +7 Unit C C C V V V V VPP VCC Device Programmer Supply Voltage Supply Voltage ESD Protection >2000 NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not recommended. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. 11.0 Operating Range Range Commercial Industrial Commercial Industrial Temperature 0 C to +70C -40 C to +85C 0 C to +70C -40 C to +85C VCC Tolerance + 5 V 10% + 5 V 10% 3.0 V to 3.6 V 3.0 V to 3.6 V 12.0 Recommended Operating Conditions Symbol VCC VCC Parameter Supply Voltage Supply Voltage Condition All Speeds V-Versions All Speeds Min 4.5 3.0 Typ 5 Max 5.5 3.6 Unit V V 73 PSD4000 Series Beta Information The following tables describe the AD/DC parameters of the PSD4000 family: AC/DC Parameters DC Electrical Specification AC Timing Specification * PLD Timing - Combinatorial Timing - Synchronous Clock Mode - Asynchronous Clock Mode - Input MicroCell Timing Microcontroller Timing - Read Timing - Write Timing - Peripheral Mode Timing - Power Down and Reset Timing * Following are issues concerning the parameters presented: In the DC specification the supply current is given for different modes of operation. Before calculating the total power consumption, determine the percentage of time that the PSD4000 is in each mode. Also, the supply power is considerably different if the Turbo bit is "OFF". The AC power component gives the PLD, Flash memory, and SRAM mA/MHz specification. Figures 32 and 32a show the PLD mA/MHz as a function of the number of Product Terms (PT) used. In the PLD timing parameters, add the required delay when Turbo bit is "OFF". Figure 32. PLD ICC /FrequencyConsumption (VCC = 5 V 10%) 110 100 90 80 ICC - (mA) 70 FF O O VCC = 5V O RB TU %) 100 N( O 60 TU 50 40 30 20 10 0 0 5 ) (25% ON BO TUR RB T UR BO OF F PT 100% PT 25% 10 15 20 25 HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz) 74 Beta Information PSD4000 Series AC/DC Parameters (cont.) Figure 32a. PLD ICC /Frequency Consumption (PSD4235G2V Versions, VCC = 3 V) 60 VCC = 3V 50 ICC - (mA) 40 OF F TU ON ( RBO 100% ) 30 20 10 TU RB O ) (25% O ON TURB TU 0 0 RB 5 O OF F PT 100% PT 25% 10 15 20 25 HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz) Example of PSD4000 Typical Power Calculation at VCC = 5.0 V Conditions Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash Access % SRAM access % I/O access Operational Modes % Normal % Power Down Mode Number of product terms used (from fitter report) % of total product terms Turbo Mode = = = = = = = = = = 8 MHz 4 MHz 80% 15% 5% (no additional power above base) 10% 90% 45 PT 45/193 = 23.3% ON Calculation (typical numbers used) ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc)) = Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE + %SRAM x 1.5 mA/MHz x Freq ALE + % PLD x 2 mA/MHz x Freq PLD + #PT x 400 A/PT = 50 A x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz + 0.15 x 1.5 mA/MHz x 4 MHz +2 mA/MHz x 8 MHz + 45 x 0.4 mA/PT) = 45 A + 0.1 x (8 + 0.9 + 16 + 18 mA) = 45 A + 0.1 x 42.9 = 45 A + 4.29 mA = 4.34 mA This is the operating power with no Flash writes or erases. Calculation is based on IOUT = 0 mA. 75 PSD4000 Series Beta Information AC/DC Parameters (cont.) Example of Typical Power Calculation at VCC = 5.0 V in Turbo Off Mode Conditions Highest Composite PLD input frequency (Freq PLD) = MCU ALE frequency (Freq ALE) % Flash Access % SRAM access % I/O access Operational Modes % Normal % Power Down Mode Number of product terms used (from fitter report) % of total product terms Turbo Mode = = = = = = = = = 8 MHz 4 MHz 80% 15% 5% (no additional power above base) 10% 90% 45 PT 45/193 = 23.3% Off Calculation (typical numbers used) ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc)) = Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE + %SRAM x 1.5 mA/MHz x Freq ALE + % PLD x (from graph using Freq PLD)) = 50 A x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz + 0.15 x 1.5 mA/MHz x 4 MHz + 24 mA) = 45 A + 0.1 x (8 + 0.9 + 24) = 45 A + 0.1 x 32.9 = 45 A + 3.29 mA = 3.34 mA This is the operating power with no Flash writes or erases. Calculation is based on IOUT = 0 mA. 76 Beta Information PSD4000 Series (5 V 10% Versions) PSD4000 DC Characteristics Symbol VCC VIH VIL VIH1 VIL1 VHYS VLKO VOL Parameter Supply Voltage High Level Input Voltage Low Level Input Voltage Reset High Level Input Voltage Reset Low Level Input Voltage Reset Pin Hysteresis VCC Min for Flash Erase and Program Output Low Voltage Conditions All Speeds 4.5 V < VCC < 5.5 V 4.5 V < VCC < 5.5 V (Note 1) (Note 1) Min 4.5 2 -.5 .8 VCC -.5 0.3 2.5 Typ 5 Max 5.5 VCC +.5 0.8 VCC +.5 .2 VCC -.1 4.2 Unit V V V V V V V V V V V V IOL = 20 A, VCC = 4.5 V IOL = 8 mA, VCC = 4.5 V 0.01 0.25 4.4 2.4 VSBY - 0.8 2.0 4.49 3.9 0.1 0.45 VOH VOH1 VSBY ISBY IIDLE VDF ISB ILI ILO IO Output High Voltage Except VSTBY On Output High Voltage VSTBY On SRAM Standby Voltage SRAM Standby Current (VSTBY Pin) Idle Current (VSTBY Pin) SRAM Data Retention Voltage Standby Supply Current for Power Down Mode Input Leakage Current Output Leakage Current Output Current IOH = -20 A, VCC = 4.5 V IOH = -2 mA, VCC = 4.5 V IOH1 = -1 A VCC = 0 V VCC > VSBY Only on VSTBY CSI > VCC -0.3 V (Notes 2, 3 and 5) VSS < VIN < VCC 0.45 < VIN < VCC Refer to IOL and IOH in the VOL and VOH row PLD_TURBO = OFF, f = 0 MHz (Note 3) VCC 0.5 1 0.1 V A A V -0.1 2 100 -1 -10 .1 5 200 1 10 A A A 0 400 15 0 0 Fig. 32 (Note 4) 2.5 1.5 3.5 3.0 700 30 0 0 mA A/PT mA mA mA PLD Only ICC (DC) (Note 5) Operating Supply Current Flash PLD_TURBO = ON, f = 0 MHz During Flash Write/Erase Only Read Only, f = 0 MHz SRAM PLD AC Base ICC (AC) (Note 5) FLASH AC Adder SRAM AC Adder NOTE: 1. 2. 3. 4. 5. f = 0 MHz mA/MHz mA/MHz Reset input has hysteresis. VIL1 is valid at or below .2VCC -.1. VIH1 is valid at or above .8VCC. CSI deselected or internal Power Down mode is active. PLD is in non-turbo mode and none of the inputs are switching Refer to Figure 32 for PLD current calculation. I O = 0 mA 77 PSD4000 Series Beta Information PSD4000 AC/DC Parameters - CPLD Timing Parameters (5 V 10% Versions) CPLD Combinatorial Timing (5 V 10%) -70 -90 Fast PT Aloc TURBO OFF Slew Rate (Note 1) Symbol t PD t EA t ER t ARP t ARPW Parameter CPLD Input Pin/Feedback to CPLD Combinatorial Output CPLD Input to CPLD Output Enable CPLD Input to CPLD Output Disable CPLD Register Clear or Preset Delay CPLD Register Clear or Preset Pulse Width CPLD Array Delay Conditions Min Max 20 21 21 21 Min Max 25 26 26 26 Unit ns ns ns ns ns ns Add 2 Add 10 Sub 2 Add 10 Sub 2 Add 10 Sub 2 Add 10 Sub 2 Add 10 10 Any MicroCell 11 20 16 Add 2 t ARD NOTE: 1. Fast Slew Rate output available on Port C and F. CPLD MicroCell Synchronous Clock Mode Timing (5 V 10% Versions) -70 -90 Fast PT Aloc TURBO OFF Slew Rate (Note 1) Symbol Parameter Maximum Frequency External Feedback Conditions 1/(tS + t CO ) 1/(tS + t CO -10) 1/(tC H + t CL ) Min Max 40.00 66.6 83.3 Min Max 30.30 43.48 50.00 Unit MHz MHz MHz f MAX Maximum Frequency Internal Feedback ( fCNT ) Maximum Frequency Pipelined Data tS tH t CH t CL t CO t ARD t MIN Input Setup Time Input Hold Time Clock High Time Clock Low Time Clock to Output Delay CPLD Array Delay Minimum Clock Period Clock Input Clock Input Clock Input Any MicroCell tC H + t CL (Note 2) 12 0 6 6 13 11 12 15 0 10 10 18 16 20 Add 2 Add 10 ns ns ns ns Sub 2 ns ns ns Add 2 NOTES: 1. Fast Slew Rate output available on Port C and F. 2. CLKIN t CLCL = t CH + t CL. 78 Beta Information PSD4000 Series PSD4000 AC/DC Parameters - CPLD Timing Parameters (5 V 10% Versions) CPLD MicroCell Asynchronous Clock Mode Timing (5 V 10% Versions) -70 Symbol Parameter Maximum Frequency External Feedback f MAXA Maximum Frequency Internal Feedback ( fCNTA) Maximum Frequency Pipelined Data t SA t HA t CHA t CLA t COA t ARDA t MINA Input Setup Time Input Hold Time Clock Input High Time Clock Input Low Time Clock to Output Delay CPLD Array Delay Minimum Clock Period Any MicroCell 1/ fC NTA 16 -90 Min Max 26.32 35.71 41.67 8 12 12 12 21 11 28 30 16 Add 2 Add 10 Add 10 Add 10 Sub 2 Add 2 Add 10 Conditions 1/(tS A + t CO A ) 1/(tS A + t CO A -10) 1/(tC H A+ t CLA) Min Max 38.4 62.5 71.4 PT Aloc TURBO OFF Slew Rate Unit MHz MHz MHz ns ns ns ns ns ns ns 6 5 9 9 Input MicroCell Timing (5 V 10% Versions) -70 Symbol t IS t IH t INH t IN L t INO -90 Min 0 20 12 12 34 46 Add 2 Add 10 Add 10 Parameter Input Setup Time Input Hold Time NIB Input High Time NIB Input Low Time NIB Input to Combinatorial Delay Conditions (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Min 0 15 9 9 Max Max PT Aloc TURBO OFF Unit ns ns ns ns ns NOTE: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX. 79 PSD4000 Series Beta Information Microcontroller Interface - AC/DC Parameters (5V 10% Versions) AC Symbols for PLD Timing. Example: A C D E I L N P R S T W B M - - - - - - - - - - - - - - t AVLX - Time from Address Valid to ALE Invalid. Signal Letters Address Input CEout Output Input Data E Input Interrupt Input ALE Input Reset Input or Output Port Signal Output UDS, LDS, DS, RD, PSEN Inputs Chip Select Input R/W Input WR Input Vstby Output Output MicroCell Signal Behavior t L H V X Z PW - - - - - - - Time Logic Level Low or ALE Logic Level High Valid No Longer a Valid Logic Level Float Pulse Width 80 Beta Information PSD4000 Series Microcontroller Interface - PSD4000 AC/DC Parameters (5V 10% Versions) Read Timing (5 V 10% Versions) -70 Symbol t LVLX t AVLX t LXAX t AVQV t SLQV t RLQV t RHQX t RLRH t RHQZ t EHEL t THEH t ELTL t AVPV NOTES: 1. 2. 3. 4. 5. -90 Min 20 6 8 70 75 24 31 90 100 32 38 0 32 20 25 32 10 0 20 25 Parameter ALE or AS Pulse Width Address Setup Time Address Hold Time Address Valid to Data Valid CS Valid to Data Valid RD to Data Valid RD or PSEN to Data Valid, 80C51XA Mode RD Data Hold Time RD Pulse Width RD to Data High-Z E Pulse Width R/W Setup Time to Enable R/W Hold Time After Enable Address Input Valid to Address Output Delay Conditions (Note 3) (Note 3) (Note 3) (Note 5) (Note 2) (Note 1) (Note 1) (Note 1) Min 15 4 5 Max Max Turbo Off Unit ns ns ns Add 10** ns ns ns ns ns ns ns ns ns ns ns 0 27 27 6 0 (Note 4) RD timing has the same timing as DS, LDS, UDS, and PSEN signals. RD and PSEN have the same timing. Any input used to select an internal PSD4000 function. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port. RD timing has the same timing as DS, LDS, and UDS signals. 81 PSD4000 Series Beta Information Microcontroller Interface - PSD4000 AC/DC Parameters (5V 10% Versions) Write Timing (5 V 10% Versions) -70 Symbol t LVLX t AVLX t LXAX t AVWL t SLWL t DVWH t WHDX t WLWH t WHAX1 t WHAX2 t WHPV t WLMV t DVMV t AVPV NOTES: 1. 2. 3. 4. 5. 6. -90 Min 20 6 8 15 15 35 5 35 8 0 27 48 42 30 55 55 ns ns ns ns ns ns ns ns ns ns ns ns Parameter ALE or AS Pulse Width Address Setup Time Address Hold Time Address Valid to Leading Edge of WR CS Valid to Leading Edge of WR WR Data Setup Time WR Data Hold Time WR Pulse Width Trailing Edge of WR to Address Invalid Trailing Edge of WR to DPLD Address Input Invalid Trailing Edge of WR to Port Output Valid Using I/O Port Data Register WR Valid to Port Output Valid Using MicroCell Register Preset/Clear Data Valid to Port Output Valid Using MicroCell Register Preset/Clear Address Input Valid to Address Output Delay Conditions (Note 1) (Note 1) (Notes 1 and 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3 and 6) (Note 3) (Notes 3 and 4) (Notes 3 and 5) Min 15 4 5 8 12 25 4 25 6 0 Max Max Unit (Note 2) 20 25 ns Any input used to select an internal PSD4000 function. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port. WR timing has the same timing as E, DS, LDS, UDS, WRL, and WRH signals. Assuming data is stable before active write signal. Assuming write is active before data becomes valid. tWHAX2 is Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory. 82 Beta Information PSD4000 Series Microcontroller Interface - PSD4000 AC/DC Parameters (5V 10% Versions) Port F Peripheral Data Mode Read Timing (5 V 10%) -70 Symbol t AVQV (PF) t SLQV (PF) t RLQV (PF) t DVQV (PF) t QXRH (PF) t RLRH (PF) t RHQZ (PF) -90 Min Max 35 35 32 38 30 0 32 23 25 Parameter Address Valid to Data Valid CSI Valid to Data Valid RD to Data Valid RD to Data Valid 8031 Mode Data In to Data Out Valid RD Data Hold Time RD Pulse Width RD to Data High-Z Conditions (Note 3) Min Max 25 25 Turbo Off Add 10 Add 10 Unit ns ns ns ns ns ns ns ns (Notes 1 and 4) 21 31 22 0 (Note 1) (Note 1) 27 Port F Peripheral Data Mode Write Timing (5 V 10%) -70 Symbol t WLQV (PF) t DVQV (PF) t WHQZ (PF) NOTES: 1. 2. 3. 4. 5. -90 Min Max 35 30 25 Parameter WR to Data Propagation Delay Data to Port F Data Propagation Delay WR Invalid to Port F Tri-state Conditions (Note 2) (Note 5) (Note 2) Min Max 25 22 20 Unit ns ns ns RD timing has the same timing as DS, LDS, UDS, and PSEN signals. WR timing has the same timing as E, DS, LDS, UDS, WRL, and WRH signals. Any input used to select Port F Data Peripheral Mode. Data is already stable on Port F. Data stable on ADIO pins to data on Port F. 83 PSD4000 Series Beta Information Microcontroller Interface - PSD4000 AC/DC Parameters (5V 10% Versions) Power Down Timing (5 V 10%) -70 Symbol t LVDV -90 Min Max 90 Parameter ALE Access Time from Power Down Maximum Delay from APD Enable to Internal PDN Valid Signal Conditions Min Max 80 Unit ns s t CLWH Using CLKIN Input 15 * t CLCL (s) (Note 1) NOTE: 1. t CLCL is the CLKIN clock period. Vstbyon Timing (5 V 10%) Symbol t BVBH t BXBL Parameter Vstby Detection to Vstbyon Output High Vstby Off Detection to Vstbyon Output Low Conditions (Note 1) (Note 1) Min Typ 20 20 Max Unit s s NOTE: 1. Vstbyon is measured at VCC ramp rate of 2 ms. Reset Pin Timing (5 V 10%) Symbol t NLNH t OPR t NLNH-PO t NLNH-A Parameter Warm RESET Active Low Time (Note 1) RESET High to Operational Device Power On Reset Active Low Time Warm RESET Active Low Time (Note 2) Conditions Min 150 Typ Max Unit ns 120 1 25 ns ms s NOTE: 1. RESET will not abort Flash programming/erase cycles. 2. RESET will abort Flash programming or erase cycle. 84 Beta Information PSD4000 Series Microcontroller Interface - PSD4000 AC/DC Parameters (5V 10% Versions) Flash Program, Write and Erase Times (5 V 10%) Symbol Parameter Flash Program Flash Bulk Erase (Preprogrammed to 00) (Note 1) Flash Bulk Erase t WHQV3 t WHQV2 t WHQV1 t WHWLO t Q7VQV Sector Erase (Preprogrammed to 00) Sector Erase Word Program Program/Erase Cycles (Per Sector) Sector Erase Time-Out DQ7 Valid to Output Valid (Data Polling) (Notes 2 and 3) 100,000 100 30 Min Typ 8.5 3 10 1 2.2 14 Max Unit sec 30 30 1200 sec sec sec sec s cycles s ns NOTE: 1. Programmed to all zeros before erase. 2. The polling status DQ7 is valid tQ7VQV ns before the data DQ0-7 is valid for reading. 3. DQ7 is DQ15 for Motorola MCU with 16-bit data bus. ISC Timing (5 V 10%) -70 Symbol t ISCCF t ISCCH t ISCCL t ISCCF-P t ISCCH-P t ISCCL-P t ISCPSU t ISCPH t ISCPCO t ISCPZV t ISCPVZ -90 Min Max 18 26 26 2 2 240 240 8 5 21 21 21 23 23 23 Parameter TCK Clock Frequency (except for PLD) TCK Clock High Time TCK Clock Low Time TCK Clock Frequency (for PLD only) TCK Clock High Time(for PLD only) TCK Clock Low Time(for PLD only) ISC Port Set Up Time ISC Port Hold Up Time ISC Port Clock to Output ISC Port High-Impedance to Valid Output ISC Port Valid Output to High-Impedance Conditions (Note 1) (Note 1) (Note 1) (Note 2) (Note 2) (Note 2) Min Max 20 Unit MHz ns ns MHz ns ns ns ns ns ns ns 23 23 240 240 6 5 NOTES: 1. For "non-PLD" programming, erase or in ISC by-pass mode. 2. For program or erase PLD only. 85 PSD4000 Series Beta Information (3.0 V to 3.6 V Versions) PSD4000 DC Characteristics Symbol VCC VIH VIL VIH1 VIL1 VHYS VLKO VOL Advance Information Min 3.0 .7 VCC -.5 .8 VCC -.5 0.3 1.5 2.2 0.01 0.15 2.9 2.7 VSBY - 0.8 2.0 VCC 0.5 -0.1 2 50 -1 -10 .1 5 100 1 10 1 0.1 2.99 2.8 0.1 0.45 Parameter Supply Voltage High Level Input Voltage Low Level Input Voltage Reset High Level Input Voltage Reset Low Level Input Voltage Reset Pin Hysteresis VCC Min for Flash Erase and Program Output Low Voltage Conditions All Speeds 3.0 V < VCC < 3.6 V 3.0 V < VCC < 3.6 V (Note 1) (Note 1) Typ Max 3.6 VCC +.5 0.8 VCC +.5 .2 VCC -.1 Unit V V V V V V V V V V V V V A A V A A A IOL = 20 A, VCC = 3.0 V IOL = 4 mA, VCC = 3.0 V VOH VOH1 VSBY ISBY IIDLE VDF ISB ILI ILO IO Output High Voltage Except VSTBY On Output High Voltage VSTBY On SRAM Standby Voltage SRAM Standby Current (VSTBY Pin) Idle Current (VSTBY Pin) SRAM Data Retention Voltage Standby Supply Current for Power Down Mode Input Leakage Current Output Leakage Current Output Current IOH = -20 A, VCC = 3.0 V IOH = -1 mA, VCC = 3.0 V IOH1 = -1 A VCC = 0 V VCC > VSBY Only on VSTBY CSI >VCC -0.3 V (Notes 2 and 3) VSS < VIN < VCC 0.45 < VIN < VCC Refer to IOL and IOH in the VOL and VOH row ZPLD_TURBO = OFF, f = 0 MHz (Note 3) 0 200 10 0 0 (Note 4) 1.5 0.8 2.0 1.5 400 25 0 0 mA A/PT mA mA mA Figure 32a mA/MHz mA/MHz PLD Only ICC (DC) (Note 5) Operating Supply Current FLASH ZPLD_TURBO = ON, f = 0 MHz During FLASH Write/Erase Only Read Only, f = 0 MHz SRAM PLD AC Base ICC (AC) (Note 5) FLASH AC Adder SRAM AC Adder NOTES: 1. 2. 3. 4. 5. f = 0 MHz Reset input has hysteresis. VIL1 is valid at or below .2VCC -.1. VIH1 is valid at or above .8VCC. CSI deselected or internal PD mode is active. PLD is in non-turbo mode and none of the inputs are switching. Refer to Figure 31a for PLD current calculation. I O = 0 mA. 86 Beta Information PSD4000 Series PSD4000 AC/DC Parameters - CPLD Timing Parameters (3.0 V to 3.6 V Versions) CPLD Combinatorial Timing (3.0 V to 3.6 V Versions) -90 Symbol t PD t EA t ER t ARP t ARPW t ARD -12 Min Max 43 45 45 43 30 23 27 Add 4 Parameter CPLD Input Pin/Feedback to CPLD Combinatorial Output CPLD Input to CPLD Output Enable CPLD Input to CPLD Output Disable CPLD Register Clear or Preset Delay CPLD Register Clear or Preset Pulse Width CPLD Array Delay Conditions Min Max 38 43 43 38 PT Aloc TURBO OFF Slew Rate (Note 1) Unit ns ns ns ns ns ns Add 4 Add 20 Sub 6 Add 20 Sub 6 Add 20 Sub 6 Add 20 Sub 6 Add 20 28 Any MicroCell NOTE: 1. Fast Slew Rate output available on Port C and F. CPLD MicroCell Synchronous Clock Mode Timing (3.0 V to 3.6 V Versions) -90 -12 PT Aloc TURBO OFF Slew Rate (Note 1) Symbol Parameter Maximum Frequency External Feedback Conditions 1/(tS + t CO ) 1/(tS + t CO -10) 1/(tC H + t CL ) Min Max 24.3 32.2 45.0 Min Max 20.4 25.6 35.7 Unit MHz MHz MHz f MAX Maximum Frequency Internal Feedback ( fCNT ) Maximum Frequency Pipelined Data tS tH t CH t CL t CO t ARD t MIN Input Setup Time Input Hold Time Clock High Time Clock Low Time Clock to Output Delay CPLD Array Delay Minimum Clock Period Clock Input Clock Input Clock Input Any MicroCell tC H + t CL (Note 2) 18 0 11 11 23 20 22 23 0 14 14 26 27 28 Add 4 Add 20 ns ns ns ns Sub 6 ns ns ns Add 4 NOTES: 1. Fast Slew Rate output available on Port C and F. 2. CLKIN tCLCL = tCH + tCL. 87 PSD4000 Series Beta Information PSD4000 AC/DC Parameters - CPLD Timing Parameters (3.0 V to 3.6 V Versions) CPLD MicroCell Asynchronous Clock Mode Timing (3.0 V to 3.6 V Versions) -90 Symbol Parameter Maximum Frequency External Feedback f MAXA Maximum Frequency Internal Feedback ( fCNTA) Maximum Frequency Pipelined Data t SA t HA t CHA t CLA t COA t ARD t MINA Input Setup Time Input Hold Time Clock High Time Clock Low Time Clock to Output Delay CPLD Array Delay Minimum Clock Period Any MicroCell 1/ fC NTA 32 -12 Min Max 20.8 26.3 30.3 10 12 18 15 34 20 38 38 26 Add 4 Add 20 Add 20 Add 20 Sub 6 Add 4 Add 20 Conditions 1/(tS A + t CO A ) 1/(tS A + t CO A -10) 1/(tC H A+ t CLA) Min Max 23.8 31.25 38.4 PT Aloc TURBO OFF Slew Rate Unit MHz MHz MHz ns ns ns ns ns ns ns 8 10 14 12 Input MicroCell Timing (3.0 V to 3.6 V Versions) -90 Symbol t IS t IH t INH t IN L t INO -12 Min 0 23 13 13 46 62 Add 4 Add 20 Add 20 Parameter Input Setup Time Input Hold Time NIB Input High Time NIB Input Low Time NIB Input to Combinatorial Delay Conditions (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Min 0 20 12 12 Max Max PT Aloc TURBO OFF Unit ns ns ns ns ns NOTE: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX. 88 Beta Information PSD4000 Series Microcontroller Interface - PSD4000 AC/DC Parameters (3.0 V to 3.6 V Versions) AC Symbols for PLD Timing. Example: A C D E G I L N P Q R S T W B M - - - - - - - - - - - - - - - - t AVLX - Time from Address Valid to ALE Invalid. Signal Letters Address Input CEout Output Input Data E Input Internal WDOG_ON signal Interrupt Input ALE Input Reset Input or Output Port Signal Output Output Data WR, UDS, LDS, DS, IORD, PSEN Inputs Chip Select Input R/W Input Internal PDN Signal Vstby Output Output MicroCell Signal Behavior t L H V X Z PW - - - - - - - Time Logic Level Low or ALE Logic Level High Valid No Longer a Valid Logic Level Float Pulse Width 89 PSD4000 Series Beta Information Microcontroller Interface - PSD4000 AC/DC Parameters (3.0 V to 3.6 V Versions) Read Timing (3.0 V to 3.6 V Versions) -90 Symbol t LVLX t AVLX t LXAX t AVQV t SLQV t RLQV t RHQX t RLRH t RHQZ t EHEL t THEH t ELTL t AVPV NOTES: 1. 2. 3. 4. 5. -12 Min 24 9 10 90 90 35 45 Parameter ALE or AS Pulse Width Address Setup Time Address Hold Time Address Valid to Data Valid CS Valid to Data Valid RD to Data Valid RD or PSEN to Data Valid, 80C51XA Mode RD Data Hold Time RD Pulse Width RD to Data High-Z E Pulse Width R/W Setup Time to Enable R/W Hold Time After Enable Address Input Valid to Address Output Delay Conditions (Note 3) (Note 3) (Note 3) (Note 5) (Note 2) (Note 1) (Note 1) (Note 1) Min 22 7 8 Max Max Turbo Off Unit ns ns ns 120 Add 20** 120 35 48 0 40 ns ns ns ns ns ns 0 36 38 38 10 0 40 42 16 0 ns ns ns ns (Note 4) 30 35 ns RD timing has the same timing as DS, LDS, UDS, and PSEN signals. RD and PSEN have the same timing for 80C51XA. Any input used to select an internal PSD4235G2V function. In multiplexed mode latched address generated from ADIO delay to address output on any Port. RD timing has the same timing as DS, LDS, and UDS signals. 90 Beta Information PSD4000 Series Microcontroller Interface - PSD4000 AC/DC Parameters (3.0 V to 3.6 V Versions) Write Timing (3.0 V to 3.6 V Versions) -90 Symbol t LVLX t AVLX t LXAX t AVWL t SLWL t DVWH t WHDX t WLWH t WHAX1 t WHAX2 t WHPV t WLMV t DVMV t AVPV NOTES: 1. 2. 3. 4. 5. 6. -12 Min 24 9 10 18 18 45 8 45 10 0 30 65 65 30 33 70 68 35 ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter ALE or AS Pulse Width Address Setup Time Address Hold Time Address Valid to Leading Edge of WR CS Valid to Leading Edge of WR WR Data Setup Time WR Data Hold Time WR Pulse Width Trailing Edge of WR to Address Invalid Trailing Edge of WR to DPLD Address Input Invalid Trailing Edge of WR to Port Output Valid Using I/O Port Data Register WR Valid to Port Output Valid Using MicroCell Register Preset/Clear Data Valid to Port Output Valid Using MicroCell Register Preset/Clear Address Input Valid to Address Output Delay Conditions (Note 1) (Note 1) (Notes 1 and 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Notes 3 and 6) (Note 3) (Notes 3 and 4) (Notes 3 and 5) (Note 2) Min 22 7 8 15 15 40 5 40 8 0 Max Max Unit Any input used to select an internal PSD4000 function. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port. WR timing has the same timing as E, DS, LDS, UDS, WRL, and WRH signals. Assuming data is stable before active write signal. Assuming write is active before data becomes valid. tWHAX2 is Address hold time for DPLD inputs that are used to generate chip selects for internal PSD memory. 91 PSD4000 Series Beta Information Microcontroller Interface - PSD4000 AC/DC Parameters (3.0 V to 3.6 V Versions) Port F Peripheral Data Mode Read Timing (3.0 V to 3.6 V Versions) -90 Symbol t AVQV (PF) t SLQV (PF) t RLQV (PF) t DVQV (PF) t QXRH (PF) t RLRH (PF) t RHQZ (PF) -12 Min Max 40 40 40 45 38 0 36 38 40 Parameter Address Valid to Data Valid CSI Valid to Data Valid RD to Data Valid RD to Data Valid, 80C51XA Mode Data In to Data Out Valid RD Data Hold Time RD Pulse Width RD to Data High-Z Conditions (Note 3) (Notes 1 and 4) Min Max 35 35 35 45 34 Turbo Off Add 20 Add 20 Unit ns ns ns ns ns ns ns ns 0 (Note 1) (Note 1) 35 Port F Peripheral Data Mode Write Timing (3.0 V to 3.6 V Versions) -90 Symbol t WLQV (PF) t DVQV (PF) t WHQZ (PF) NOTES: 1. 2. 3. 4. 5. -12 Min Max 43 38 33 Parameter WR to Data Propagation Delay Data to Port F Data Propagation Delay WR Invalid to Port F Tri-state Conditions (Note 2) (Note 5) (Note 2) Min Max 40 35 33 Unit ns ns ns RD timing has the same timing as DS, LDS, UDS, and PSEN signals. WR timing has the same timing as E, DS LDS, UDS, WRL, and WRH signals. Any input used to select Port F Data Peripheral Mode. Data is already stable on Port F. Data stable on ADIO pins to data on Port F. 92 Beta Information PSD4000 Series Microcontroller Interface - PSD4000 AC/DC Parameters (3.0 V to 3.6 V Versions) Power Down Timing (3.0 V to 3.6 V Versions) -90 Symbol t LVDV t CLWH -12 Min Max 135 Parameter ALE Access Time from Power Down Maximum Delay from APD Enable to Internal PDN Valid Signal Conditions Min Max 128 Unit ns s Using CLKIN Input 15 * t CLCL (s) (Note 1) NOTE: 1. tCLCL is the CLKIN clock period. Vstbyon Timing (3.0 V to 3.6 V Versions) Symbol t BVBH t BXBL Parameter Vstby Detection to Vstbyon Output High Vstby Off Detection to Vstbyon Output Low Conditions (Note 1) (Note 1) Min Typ 20 20 Max Unit s s NOTE: 1. Vstbyon is measured at VCC ramp rate of 2 ms. Reset Pin Timing (3.0 V to 3.6 V Versions) Symbol t NLNH t OPR t NLNH-PO t NLNH-A Parameter Warm RESET Active Low Time (Note 1) RESET High to Operational Device Power On Reset Active Low Time Warm RESETActive Low Time (Note 2) Conditions Min 300 Typ Max Unit ns 300 1 25 ns ms s NOTE: 1. RESET will not abort Flash programming/erase cycles. 2. RESET will abort Flash programming or erase cycle. 93 PSD4000 Series Beta Information Microcontroller Interface - PSD4000 AC/DC Parameters (3.0 V to 3.6 V Versions) Flash Program, Write and Erase Times (3.0 V to 3.6 V Versions) Symbol Parameter Flash Program Flash Bulk Erase (Preprogrammed to 00) (Note 1) Flash Bulk Erase t WHQV3 t WHQV2 t WHQV1 t WHWLO t Q7VQV Sector Erase (Preprogrammed to 00) Sector Erase Word Program Program/Erase Cycles (Per Sector) Sector Erase Time-Out DQ7 Valid to Output Valid (Data Polling) (Notes 2 and 3) 100,000 100 30 Min Typ 8.5 3 10 1 2.2 14 Max Unit sec 30 30 1200 sec sec sec sec s cycles s ns NOTES: 1. Programmed to all zeros before erase. 2. The polling status DQ7 is valid tQ7VQV ns before the data DQ0-7 is valid for reading. 3. DQ7 is DQ15 for Motorola MCU with 16-bit data bus. ISC Timing (3.0 V to 3.6 V Versions) -90 Symbol t ISCCF t ISCCH t ISCCL t ISCCF-P t ISCCH-P t ISCCL-P t ISCPSU t ISCPH t ISCPCO t ISCPZV -12 Min Max 12 40 40 2 2 240 240 12 5 26 26 26 32 32 32 Parameter TCK Clock Frequency (except for PLD) TCK Clock High Time TCK Clock Low Time TCK Clock Frequency (for PLD only) TCK Clock High Time (for PLD only) TCK Clock Low Time (for PLD only) ISC Port Set Up Time ISC Port Hold Up Time ISC Port Clock to Output ISC Port High-Impedance to Valid Output Conditions (Note 1) (Note 1) (Note 1) (Note 2) (Note 2) (Note 2) Min Max 15 Unit MHz ns ns MHz ns ns ns ns ns ns ns 30 30 240 240 11 5 ISC Port Valid Output to High-Impedance t ISCPVZ NOTES: 1. For "non-PLD" programming, erase or in ISC by-pass mode. 2. For program or erase PLD only. 94 Beta Information PSD4000 Series Figure 33. Read Timing tAVLX ALE/AS tLVLX A/D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS tLXAX* ADDRESS VALID tAVQV ADDRESS VALID DATA VALID DATA VALID tSLQV CSI tRLQV tRLRH RD (PSEN, DS) tRHQZ tRHQX tEHEL E tTHEH tELTL R/W tAVPV ADDRESS OUT *tAVLX and tLXAX are not required 80C51XA in Burst Mode. 95 PSD4000 Series Beta Information Figure 34. Write Timing tAVLX ALE/AS t LXAX t LVLX A/D MULTIPLEXED BUS ADDRESS VALID tAVWL ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS tSLWL CSI tDVWH WR (DS) t WLWH t WHDX t WHAX ADDRESS VALID DATA VALID DATA VALID t EHEL E t THEH R/ W t WLMV tAVPV ADDRESS OUT t WHPV STANDARD MCU I/O OUT t ELTL 96 Beta Information PSD4000 Series Figure 35. Peripheral I/O Read Timing ALE/AS A/D BUS ADDRESS DATA VALID tAVQV (PF) tSLQV (PF) CSI tRLQV (PF) RD tRLRH (PF) tQXRH (PA) tRHQZ (PA) tDVQV (PF) DATA ON PORT F Figure 36. Peripheral I/O Write Timing ALE/AS A / D BUS ADDRESS DATA OUT tWLQV WR (PF) tWHQZ (PF) tDVQV (PF) PORT F DATA OUT 97 PSD4000 Series Beta Information Figure 37. Combinatorial Timing - PLD CPLD INPUT t PD CPLD OUTPUT Figure 38. Synchronous Clock Mode Timing - PLD tCH tCL CLKIN tS INPUT tH tCO REGISTERED OUTPUT 98 Beta Information PSD4000 Series Figure 39. Asynchronous Clock Mode Timing (Product-Term Clock) tCHA tCLA CLOCK tSA tHA INPUT tCOA REGISTERED OUTPUT Figure 40. Input MicroCell Timing (Product-Term Clock) t INH PT CLOCK t INL t IS INPUT t IH OUTPUT t INO 99 PSD4000 Series Beta Information Figure 41. Input to Output Disable/ Enable INPUT tER INPUT TO OUTPUT ENABLE/DISABLE tEA Figure 42. Asynchronous Reset/ Preset tARPW RESET/PRESET INPUT tARP REGISTER OUTPUT Figure 43. ISC Timing t ISCCH TCK t ISCCL t ISCPSU t ISCPH TDI/TMS t ISCPZV t ISCPCO ISC OUTPUTS/TDO t ISCPVZ ISC OUTPUTS/TDO 100 Beta Information PSD4000 Series Figure 44. Reset Timing OPERATING LEVEL t NLNH-PO VCC t NLNH t NLNH-A RESET t OPR POWER ON RESET WARM RESET t OPR Figure 45. Key to Switching Waveforms WAVEFORMS INPUTS OUTPUTS STEADY INPUT STEADY OUTPUT MAY CHANGE FROM HI TO LO MAY CHANGE FROM LO TO HI WILL BE CHANGING FROM HI TO LO WILL BE CHANGING LO TO HI DON'T CARE CHANGING, STATE UNKNOWN OUTPUTS ONLY CENTER LINE IS TRI-STATE 101 PSD4000 Series Beta Information TA = 25 C, f = 1 MHz 14.0 Pin Capacitance Symbol CIN COUT CVPP Parameter 1 Capacitance (for input pins only) Capacitance (for input/output pins) Capacitance (for CNTL2/VPP) Conditions Typical 2 Max Unit VIN = 0 V VOUT = 0 V VPP = 0 V 4 8 18 6 12 25 pF pF pF NOTES: 1. These parameters are only sampled and are not 100% tested. 2. Typical values are for TA = 25C and nominal supply voltages. 15.0 Figure 46. AC Testing Input/Output Waveform 3.0V TEST POINT 0V 1.5V 16.0 Figure 47. AC Testing Load Circuit DEVICE UNDER TEST 2.01 V 195 CL = 30 pF (INCLUDING SCOPE AND JIG CAPACITANCE) 17.0 Programming Upon delivery from Waferscale, the PSD4000 device has all bits in the PLDs and memories in the "1" or high state. The configuration bits are in the "0" or low state. The code, configuration, and PLDs logic are loaded through the procedure of programming. Information for programming the device is available directly from Waferscale. Please contact your local sales representative. (See the last page.) 102 Beta Information PSD4000 Series 18.0 PSD4000 Pin Assignments 80-Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Assignments PD2 PD3 AD0 AD1 AD2 AD3 AD4 GND VCC AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 VCC GND PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 RESET CNTL2 Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin Assignments PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 GND GND PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 CNTL0 CNTL1 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VCC GND PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PD0 PD1 103 PSD4000 Series Beta Information 70 GND 69 VCC 68 PB7 67 PB6 66 PB5 65 PB4 64 PB3 63 PB2 62 PB1 61 PB0 80 PD1 79 PD0 78 PE7 77 PE6 76 PE5 75 PE4 74 PE3 73 PE2 72 PE1 71 PE0 19.0 PSD4000 Package Information Figure 48. Drawing U5 - 80-Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) PD2 PD3 AD0 AD1 AD2 AD3 AD4 VCC AD5 AD6 AD7 AD8 AD9 1 2 3 4 5 6 7 9 10 11 12 13 14 60 CNTL1 59 CNTL0 58 PA7 57 PA6 56 PA5 55 PA4 54 PA3 53 PA2 52 PA1 51 PA0 50 GND 49 GND 48 PC7 47 PC6 46 PC5 45 PC4 44 PC3 43 PC2 42 PC1 41 PC0 GND 8 AD10 15 AD11 16 AD12 17 AD13 18 AD14 19 AD15 20 PG0 21 PG1 22 PG2 23 PG3 24 PG4 25 PG5 26 PG6 27 PG7 28 VCC 29 GND 30 PF0 31 PF1 32 PF2 33 PF3 34 PF4 35 PF5 36 PF6 37 PF7 38 RESET 39 104 CNTL2 40 Beta Information PSD4000 Series Figure 48A. Drawing U5 - 80-Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) D D1 D3 80 1 2 3 Index Mark E3 E1 E Standoff: 0.05 mm Min. A1 A2 A C L B e1 Load Coplanarity: 0.102 mm Max. Family: Plastic Thin Quad Flatpack (TQFP) Millimeters Symbol A A2 B C D D1 D3 E E1 E3 e1 L N 0.45 80 13.95 11.95 9.5 0.50 0.75 13.95 11.95 9.5 14.05 12.05 Reference Reference 0.018 80 060198R0 Inches Notes Min 0 - 0.037 Reference 0.007 0.512 0.433 Reference 0.512 0.433 0.374 0.019 0.030 0.374 0.551 0.472 Reference Reference Min 0 - 0.95 0.17 Max 7 1.20 1.05 0.27 0.20 14.05 12.05 Max 8 0.047 0.041 0.011 0.008 0.551 0.472 Notes Reference 105 106 PSD4000 Series 20.0 Selector Guide Selector Guide - PSD4000 Series Part # 5 Volts Data Path MCU PLDs/Decoders I/O Memory Other Software PSDsoft Express PSDsoft 2000 PMU APD Inputs Input Macrocells Output Macrocells Outputs Page Reg. Ports Flash Program Store ISP via JTAG 2nd Flash Array IAP via MCU EEPROM Zero Power SRAM Per. Mode w/BB Security PSD4235G2 PSD4135G2 16 57 - - 24 8-bit 52 4096Kb 256Kb - 16 57 24 16 24 8-bit 52 4096Kb 256Kb - 64Kb 64Kb X X X X X X - - X X X X X X X X Beta Information Beta Information PSD4000 Series 21.0 Part Number Construction Flash PSD Part Number Construction CHARACTER # 1 PART NUMBER I P 2 I S 3 I D 4 I 5 I 42 6 I 1 7 I 3 8 I F 9 I 10 11 12 13 14 15 16 17 18 19 I I I I I I I I I 2 -A-1 5J PSD BRAND NAME PSD = Standard Low Power Device FAMILY/SERIES 8 = Flash PSD for 8-bit MCUs 41 = Flash PSD for 16-bit MUCs (with simple PLD) 42 = Flash PSD for 16-bit MUCs (with CPLD) SRAM SIZE 0 = 0Kb 1 = 16Kb 2 = 32Kb 3 = 64Kb NVM SIZE 1 = 256Kb 2 = 512Kb 3 = 1Mb 4 = 2Mb 5 = 4Mb TEMP RANGE "Blank" = 0C to +70C (Commercial) I = -40C to +85C (Industrial) PACKAGE TYPE J = PLCC U = TQFP M = PQFP B81 = BGA SPEED - 70 = 70ns - 90 = 90ns - 12 = 120ns - 15 = 150ns - 20 = 200ns REVISION "Blank" = no rev. - A = Rev. A - B = Rev. B - C = Rev. C Vc c VOLTAGE I/O COUNT & OTHER F = 27 I/O G = 52 I/O 2ND NVM TYPE, SIZE & CONFIGURATION 1 = EEPROM, 256Kb 2 = FLASH, 256Kb 3 = No 2nd Array "blank" = 5 Volt V = 3.0 Volt 22.0 Ordering Information 107 PSD4000 Series Beta Information The following information describes exceptions to specifications contained in this data sheet. These exceptions will be corrected in future releases of PSD4135G2 and will be identified by date code. 1. The Battery Backup SRAM Feature Normal Operation - The PSD SRAM can be backed-up by an external battery in the event of a system power down or failure. This feature is enabled in PSDsoft and by connecting the battery to the Vstby pin on Port E (PE6). Automatic power switchover will occur when the system voltage level (VCC) drops below the battery voltage. Discrepancy - This feature is not functional, may cause latch up if battery is connected to pin PE6. Pin PE6 can be configured to perform other I/O functions. Do not connect the battery until the problem is fixed. The "Vbaton" function on pin PE7 is not available since the battery is not connected to the PSD. 23.0 Temporary Exceptions to Specification 108 Beta Information PSD4000 Series Document Revisions Date 1 May 00 Revision Reason PSD4235G2 Initial release - Data Sheet Changes 109 Waferscale Worldwide Sales, Service and Technical Support REPRESENTATIVES ALABAMA Rep, Inc. Tel: (256) 881-9270 Fax: (256) 882-6692 ARIZONA Summit Sales Tel: (480) 998-4850 Fax: (480) 998-5274 CALIFORNIA SC Cubed Tel: (949) 598-3900 Fax: (949) 598-3918 Tel: (818) 865-6222 Fax: (818) 865-6223 Earle Assoc., Inc. Tel: (619) 278-5441 Fax: (619) 278-5443 RSVP Associates Tel: (408) 467-1200 Fax: (408) 467-1250 Tel: (916) 567-0393 Fax: (916) 567-0393 Tel: (707) 586-1694 Fax: (707) 585-2617 CANADA Intelatech, Inc. Tel: (905) 629-0082 Fax: (905) 629-1795 COLORADO Waugaman Associates, Inc. Tel: (303) 926-0002 Fax: (303) 926-0828 CONNECTICUT Advanced Tech Sales Tel: (203) 284-8247 Fax: (203) 284-8232 FLORIDA Conley & Associates, Inc. Tel: (407) 365-9347 Fax: (407) 365-1515 Tel: (407) 365-3283 Fax: (407) 365-3727 Tel: (727) 572-8895 Fax: (727) 572-8896 GEORGIA Rep, Inc. Tel: (770) 938-4358 Fax: (770) 938-0194 IDAHO Electrodyne, Inc. Tel: (801) 264-8050 Fax: (801) 264-8065 ILLINOIS Victory Sales Tel: (630) 483-3417 Fax: (847) 963-2840 INDIANA Victory Sales Tel: (317) 581-0880 Fax: (317) 581-0882 IOWA Gassner & Clark Co. Tel: (319) 393-5763 Fax: (319) 393-5799 KANSAS/NEBRASKA Rush & West Associates Tel: (913) 764-2700 Fax: (913) 764-0096 KENTUCKY Victory Sales Tel: (937) 436-1222 Fax: (937) 436-1224 MD/VA/DE/WV Strategic Sales, Inc. Tel: (410) 995-1900 Fax: (410) 964-3364 MASSACHUSETTS Advanced Tech Sales, Inc. Tel: (978) 664-0888 Fax: (978) 664-2526 MICHIGAN Victory Sales Tel: (313) 432-3151 Fax: (313) 432-3146 MINNESOTA OHMS Technology, Inc. Tel: (612) 932-2920 Fax: (612) 932-2918 MISSOURI Rush & West Associates Tel: (734) 965-3322 Fax: (734) 965-3529 NEW JERSEY Strategic Sales, Inc. Tel: (201) 842-8960 Fax: (201) 842-0906 BGR WYCK Tel: (856) 727-1070 Fax: (856) 727-9633 NEW MEXICO Summit Sales Tel: (480) 998-4850 Fax: (480) 998-5274 NEW YORK Strategic Sales, Inc. Tel: (973) 237-9440 Fax: (973) 237-9445 Tri-Tech Electronics, Inc. Tel: (716) 385-6500 Fax: (716) 385-7655 Tel: (607) 722-3580 Fax: (607) 722-3774 NORTH CAROLINA Rep, Inc. Tel: (919) 469-9997 Fax: (919) 481-3879 OHIO Victory Sales Tel: (440) 498-7570 Fax: (440) 498-7574 Tel: (937) 436-1222 Fax: (937) 436-1224 OKLAHOMA CompTech Tel: (918) 266-1966 Fax: (918) 266-1801 OREGON I Squared, Inc. Tel: (503) 670-0557 Fax: (503) 670-7646 PENNSYLVANIA Victory Sales Tel: (440) 498-7570 Fax: (440) 498-7574 BGR WYCK Tel: (609) 727-1070 Fax: (609) 727-9633 PUERTO RICO Waferscale Sales Tel: (972) 418-2970 Fax: (972) 418-2971 SOUTH CAROLINA Rep, Inc. Tel: (919) 469-9997 Fax: (919) 481-3879 TENNESSEE Rep, Inc. Tel: (423) 475-9012 Fax: (423) 475-6340 TEXAS CompTech Sales Tel: (817) 640-8200 Fax: (817) 640-8204 UTAH Electrodyne, Inc. Tel: (801) 264-8050 Fax: (801) 264-8065 WASHINGTON I Squared, Inc. Tel: (425) 822-9220 Fax: (425) 827-0350 WISCONSIN Victory Sales Tel: (414) 789-5770 Fax: (414) 789-5760 OHMS Technology, Inc. Tel: (612) 932-2920 Fax: (612) 932-2918 WYOMING Waugaman Associates, Inc. Tel: (303) 926-0002 Fax: (303) 926-0828 BRAZIL Colgil Comercial Ltda. Tel: 011-55-11-3865-6001 Fax: 011-55-11-3666-9131 CHINA Lestina International Ltd. Tel: 8610-849-9430/8888 Fax: 8610-849-9430 Tel: 86811-531-5258 Fax: 86811-531-5258 Tel: 8620-380-7307/5688 Fax: 8620-380-7307 Tel: 8625-449-1384 Fax: 8625-449-1384 P&S Tel: (480) 633-0884 Fax: (480) 633-0885 Tel: (86) 27 7493500/3506 Fax: (86) 27 7491166 Tel: (86) 10 62549897 Fax: (86) 10 62536518 Tel: (86) 21 64714208 Fax: (86) 21 64714208 Tel: (86) 755 3245517 Fax: (86) 755 3353183 Tel: (86) 28 5575657 Fax: (86) 28 5563631 Tel: (86) 25 4508571 Fax: (86) 25 4526775 Tel: (852) 23142786 Fax: (852) 23142305 Wuhan Liyuan Comp. Tel: 86-27-7802986 Fax: 86-27-7802985 DENMARK Jakob Hatteland A/S Tel: 45-42-571000 Fax: 45-42-166199 EASTERN EUROPE Elatec Vertriebs Tel: 49-89-462-3070 Fax: 49-89-460-2403 ENGLAND Micro Call, Ltd. Tel: 44-1296-330061 Fax: 44-1296-330065 Silicon Concepts, Ltd. Tel: 44-1428-751-617 Fax: 44-1428-751-603 FINLAND Avnet Nortec OY Tel: 358-0613181 Fax: 358-06922326 FRANCE Microel Tel: 33-1-69-07-08-24 Fax: 33-1-69-07-17-23 Misil Technologies Tel: 33-1-45-60-00-21 Fax: 33-1-45-60-01-86 GERMANY Atlantik Elektronik GmbH Tel: 49-89-895050 Fax: 49-89-89505100 Scantec GmbH Tel: (49)-089 89 91 43-0 Fax: (49)-089 89 91 43-27 Topas Electronic GmbH Tel: 49-511-968640 Fax: 49-511-9686464 GREECE Radel S.A. Tel: 301-921-3058 Fax: 301-924-2835 HONG KONG Lestina International Ltd. Tel: 852-2735-1736 Fax: 852-2730-5260 INDIA/PAKISTAN Pamir Electronics Corp. (USA Office) Tel: 610-594-8337 Fax: 610-594-8559 In-Flux Tel: 65-748-9959 Fax: 65-748-9979 INDONESIA In-Flux Tel: 65-748-9959 Fax: 65-748-9979 E-Smart Distribution Pte, Ltd. Tel: 65-299-7811 Fax: 65-294-1518 ISRAEL Star-Tronics, Ltd. Tel: 972-3-6960148 Fax: 972-3-6960255 ITALY Comprel SPA Tel: 39-3625781 Fax: 39-0362496800 Silverstar Tel: 39-2661251 Fax: 39-266101359 JAPAN Internix, Inc. Tel: 813-3-369-1105 Fax: 813-3-363-8486 Kyocera Corporation Tel: 813-3-708-3111 Fax: 813-3-708-3372 Nippon Imex Corporation Tel: 813-3-321-8000 Fax: 813-3-325-0021 KOREA D&T Tel: (822) 844-2668 Fax: (822) 844-2118 MALAYSIA In-Flux Tel: 65-748-9959 Fax: 65-748-9979 E-Smart Distribution Pte, Ltd. Tel: 65-299-7811 Fax: 65-294-1518 MEXICO CompTech Sales Tel: (915) 566-1022 Fax: (52) 16-13-21-56 Tel: (52) 83-48-05-69 Fax: (52) 83-47-90-26 Tel: (52) 36-47-83-60 Fax: (52) 36-47-74-03 Tel: (52) 73-18-35-72 Fax: (52) 73-18-55-00 NETHERLANDS Alcom Electronics bv Tel: 31-10-288-2500 Fax: 31-10-288-2525 NEW ZEALAND Apex Electronics Tel: 644-3853404 Fax: 644-3853483 NORWAY Henaco A/S Tel: 47-22-917900 Fax: 47-22-917901 PHILIPPINES In-Flux Tel: 65-748-9959 Fax: 65-748-9979 REPUBLIC OF SOUTH AFRICA Components & System Design Tel: 2711-391-3062 Fax: 2711-391-5130 SINGAPORE E-Smart Distribution Pte, Ltd. Tel: 65-299-7811 Fax: 65-294-1518 SPAIN, PORTUGAL Matrix Electronica SL Tel: 34-91-5602737 Fax: 34-91-5652863 SWEDEN DipCom Electronics AB Tel: 46-8-7522480 Fax: 46-8-7513649 SWITZERLAND Elbatex Tel: 41-56-437-5111 Fax: 41-56-437-5188 Laser & Electronic AG Tel: 41-1-947-50-70 Fax: 41-1-947-50-80 TAlWAN Ally, Inc. Tel: 886-02-768-6399 Fax: 886-02-768-6390 EPCO Technology Co. Ltd. Tel: 886-02-8797-2627 Fax: 886-02-8797-2625 THAILAND In-Flux Tel: 65-748-9959 Fax: 65-748-9979 E-Smart Distribution Pte, Ltd. Tel: 65-299-7811 Fax: 65-294-1518 DISTRIBUTORS Arrow Electronics Bell Micro Products Wyle Electronics Zeus Electronics WORLDWIDE AUSTRALIA Zatek Components Tel: 61-2-9-744-5711 Fax: 61-2-9-744-5527 Tel: 61-3-9574-9644 Fax: 61-3-9574-9661 AUSTRIA Atlantic Elektronic GmbH Tel: 43-1897-2637 Fax: 43-1897-2737 BELGIUM, LUX Alcom Electronics nv/sa Tel: 32-3-458-3033 Fax: 32-3-458-3126 REGIONAL SALES Midwest Buffalo Grove, IL Tel: (847) 215-2560 Fax: (847) 215-2702 Northeast Reading, MA Tel: (781) 670-9313 Fax: (781) 670-9329 Southeast Dallas, TX Tel: (972) 292-3285 Fax: (972) 292-3610 EUROPE SALES Waferscale - Europe 2 Voie La Cardon 91126 Palaiseau Cedex, France Tel: 33 (1) 69-32-01-20 Fax: 33 (1) 69-32-02-19 ASIA SALES Waferscale - Taiwan No. 31-5, Alley 65, Lane 220, Sec. 2 Hsin-Long Road, Taipei City, Taiwan Roc Tel: 886-2-8780-2340 Fax: 886-2-8780-6751 Waferscale - Asia, Ltd. Korea Branch Tel: 82-2-761-1281/2 Fax: 82-2-761-1283 5/21/00 Corporate Headquarters 47280 Kato Road Fremont, California 94538-7333 Tel: 510-656-5400 Fax: 510-657-5916 800-TEAM-WSI (800-832-6974) Web Site: http://www.waferscale.com E-mail: info@waferscale.com Western Area Irvine, CA Tel: (949) 453-5992 Fax: (949) 453-5995 Fremont, CA Tel: (510) 498-1744 Fax: (510) 657-5916 110 |
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